Methods and apparatus for using memory
View Patent ↗In an aspect, a method is provided for using memory. The method includes the steps of (1) employing memory stacking, memory mirroring and memory interleaving in a total memory to reduce a number of memory entries that are written to an input/output (I/O) device while a portion of the total memory is replaced; and (2) storing data in the total memory. Numerous other aspects are provided.
1. A method, comprising:
employing memory stacking and memory mirroring in a total memory to reduce a number of memory entries that are written to an input/output (I/O) device while a portion of the total memory is replaced; and
storing data in the total memory;
wherein the total memory includes a first plurality of memories coupled to respective memory ports in a first group of memory ports of a memory controller and a second plurality of memories coupled to respective memory ports in a second group of memory ports of the memory controller.
2. The method of claim 1 further comprising employing memory interleaving in the total memory.
3. The method of claim 1 further comprising detecting an error in the portion of the total memory.
4. The method of claim 1 wherein employing memory stacking and memory mirroring includes employing memory stacking and memory mirroring in the total memory to reduce a number of I/O accesses while the portion of the total memory is replaced.
5. The method of claim 1 wherein employing memory stacking and memory mirroring includes employing memory stacking and memory mirroring in the total memory to reduce a number of memory entries that are written to the total memory from the I/O device after the portion of the total memory is replaced.
6. A method, comprising:
storing data in a total memory;
employing memory stacking and memory mirroring in the total memory; and
reducing a number of memory entries that are written to an input/output (I/O) device while a portion of the total memory is replaced;
wherein the total memory includes a first plurality of memories coupled to respective ports in a first group of memory ports of a memory controller and a second plurality of memories coupled to respective memory ports in a second group of memory ports of the memory controller.
7. The method of claim 6 further comprising employing memory interleaving in the total memory.
8. The method of claim 6 wherein reducing a number of memory entries that are written to an I/O device includes reducing a number of I/O accesses while the portion of the total memory is replaced.
9. An apparatus, comprising:
a processor;
an input/output (I/O) device;
a memory controller, coupled to the processor and I/O device, including a first and second group of memory ports; and
a total memory coupled to the memory controller, wherein the total memory include a first plurality of memories coupled to respective memory ports in the first group and a second plurality of memories coupled to respective memory ports in the second group;
wherein the apparatus is adapted to:
employ memory stacking and memory interleaving in the total memory to reduce a number of memory entries that are written to the input/output (I/O) device while a portion of the total memory is replaced; and
store data in the total memory.
10. The apparatus of claim 9 wherein the apparatus is further adapted to employ memory mirroring in the total memory.
11. The apparatus of claim 9 wherein the apparatus is further adapted to detect an error in the portion of the total memory.
12. The apparatus of claim 9 wherein the apparatus is further adapted to employ memory stacking and memory interleaving in the total memory to reduce a number of I/O accesses while the portion of the total memory is replaced.
13. The apparatus of claim 9 wherein the apparatus is further adapted to employ memory stacking and memory interleaving in the total memory to reduce a number of memory entries that are written to the total memory from the I/O device after the portion of the total memory is replaced.