Acyclic modeling of combinational loops
View Patent ↗Aspects of the present invention are directed to converting non-oscillatory combinational loops into acyclic circuits. Combinational loops may be modeled as state-holding elements where non-oscillatory loops are broken using edge-sensitive latches. In addition to providing a way to model combinational loops originally consisting only of gates (i.e., without originally including any state-holding elements), loops that have paths through user latches may also be converted. The presented methodology may be used with both small and large loops.
1. A method for converting a combinational loop in a circuit design into an acyclic circuit, comprising:
sending first data representing the combinational loop; and
receiving second data representing an acyclic path including at least one added state-holding element, the acyclic path being functionally equivalent to the combinational loop,
wherein the second data is generated by determining whether the combinational loop is monotonic and, responsive to a determination that the combinational loop is monotonic, transforming the combinational loop into the acyclic path by adding the at least one state-holding element, and
wherein determining whether the combinational boy is monotonic comprises
determining a function F(I), a function G(I), and a function B(I), wherein I represents at least one non-cyclic input to the loop, such that A =(F(I) AND A) OR (G(I) AND INV(A)) OR B(I), and wherein A represents a first output of the loop,
determining whether G(I) is zero or nonzero, and
determining that the combinational loop is mono tonic based on a determination that G(I) is zero.
2. The method of claim 1 , further including determining a Strongly Connected Component (SCC) of the design, wherein the combinational loop is contained in the SCC.
3. The method of claim 1 , wherein the state-holding element is a latch.
4. The method of claim 1 , wherein the combinational loop is purely combinational.
5. The method of claim 1 , wherein the combinational loop comprises a plurality of combinational elements, and the acyclic path also comprises the plurality of combinational elements.
6. A computer-assisted method for converting a combinational loop in a circuit design into an acyclic circuit, comprising:
synthesizing the combinational loop from a higher-level design description using an automated synthesis tool;
determining whether the combinational loop is monotonic by:
determining a function F(I), a function G(I), and a function B(I), wherein I represents at least one non-cyclic input to the loop, such that A =(F(I) AND A) OR (G(I) AND INV(A)) OR B(I), and wherein A represents a first output of the loop, and
determining whether G(I) is zero or nonzero,
determining that the combinational loop is mono tonic based on a determination that G(I) is zero; and
responsive to a determination that the combinational loop is monotonic, transforming the combinational loop into an acyclic path having at least one state-holding element.
7. The method of claim 6 , wherein the combinational loop comprises a plurality of combinational elements, and the acyclic path also comprises the plurality of combinational elements.
8. A computer-readable medium storing computer-executable instructions for converting a combinational loop in a circuit design into an acyclic circuit, the instructions defining steps including:
determining whether the combinational loop is monotonic by:
determining a function F(I), a function G(I), and a function B(I), wherein I represents at least one non-cyclic input to the loop, such t at A =(F(I) AND A) OR (G(I) AND INV(A)) OR B(I), and wherein A represents a first output of the loop,
determining whether G(I) is zero or nonzero,
determining that the combinational loop is monotonic based on a determination that G(I) is zero; and
responsive to a determination that the combinational loop is monotonic, transforming the combinational loop into an acyclic path by adding at least one state-holding element.
9. The computer-readable medium of claim 8 , wherein the combinational loop has a plurality of outputs including the first output, and wherein the instructions further define a step of choosing the first output to be that output that is contained in the maximum number of feedback paths in the design.
10. The computer-readable medium of claim 8 , wherein the step of transforming includes defining a value-hold condition of the state-holding element as being F(I) AND INV(B(I)).
11. The computer-readable medium of claim 8 , wherein the state-holding element is a latch.
12. The computer-readable medium method of claim 8 , wherein the instructions further define a step of notifying a user responsive to a determination that the combinational loop is not monotonic.
13. The computer-readable medium of claim 8 , wherein the instructions further define a step of determining a Strongly Connected Component (SCC) of the design, wherein the combinational loop is contained in the SCC.
14. The computer-readable medium of claim 8 , wherein the combinational loop is purely combinational.
15. The computer-readable medium of claim 8 , wherein the combinational loop comprises a plurality of combinational elements, and the acyclic path also comprises the plurality of combinational elements.