Patent Assignment
Reel/Frame 056510/0240
Merger and Change of Name
Recorded: 2021-06-02
Pages: 7
Assignors
MENTOR GRAPHICS CORPORATION
Executed: 2020-12-30
SIEMENS INDUSTRY SOFTWARE INC.
Executed: 2020-12-30
Assignee
SIEMENS INDUSTRY SOFTWARE INC.
5800 GRANITE PARKWAY, SUITE 600, PLANO, TEXAS, 75024
Covered Properties
(94)
Retiming Circuits Using a Cut-Based Approach
Built-In Self-Analyzer for Embedded Memory
Compressing Test Responses Using a Compactor
Memory Re-Implementation for Field Programmable Gate Arrays
Configurable Advanced Technology Attachement/Integrated Drive Electronics Host Controller with Programmable Timing Registers That Store Timing Parameters That Control Communications
Osculating Models for Predicting the Operation of a Circuit Structure
Testing Memories Using Algorithm Selection
Secure Exchange of Information in Electronic Design Automation
Compactor Independent Fault Diagnosis
Resource Management During System Verification
Using Constrained Scan Cells to Test Integrated Circuits
Mutual Inductance Extraction Using Dipole Approximations
Test Structures and Method for Interconnect Impedance Property Extraction
Generating Test Patterns Having Enhanced Coverage of Untargeted Defects
Loop Manipulation in a Behavioral Synthesis Tool
Combined Host Interface Controller for Conducting Communication Between a Host System and Multiple Devices in Multiple Protocols
Source Optimization for Image Fidelity and Throughput
Opc Simulation Model Using Socs Decomposition of Edge Fragments
Long Range Corrections in Integrated Circuit Layout Designs
Acyclic Modeling of Combinational Loops
Branch Merge Reduction of Rlcm Networks
Integrated Circuit Layout Design Methodology with Process Variation Bands
Metastability Effects Simulation for a Circuit Description
Chromeless Phase Shifting Mask for Integrated Circuits Using Interior Region
Managing Communication Bandwidth in Co-Verification of Circuit Designs
Software State Replay
Feature Failure Correlation
Removing the Effects of Unknown Test Values from Compacted Test Responses
Flexible Memory Built-in-Self-Test (Mbist) Method and Apparatus
Reduced-Pin-Count-Testing Architectures for Applying Test Patterns
Calculation System for Inverse Masks
Managing and Controlling the Use of Hardware Resources on Integrated Circuits
Generating Responses to Patterns Stimulating an Electronic Circuit with Timing Exception Paths
Direct Logic Diagnostics with Signature-Based Fault Dictionaries
Automating Power Domains in Electronic Design Automation
Enhanced Diagnosis with Limited Failure Cycles
Modular Compaction of Test Responses
Grid-Based Resist Simulation
Computation of Electrical Properties of an Ic Layout
Opc Conflict Identification and Edge Priority System
Selectively Reducing the Number of Cell Evaluations in a Hardware Simulation
Modeling of Systems Using Canonical Form Functions and Symbolic Regression
Speeding Up Defect Diagnosis Techniques
Extracting High Frequency Impedance in a Circuit Design Using Broadband Representations
Sum of Coherent Systems (Socs) Approximation Based on Object Information
Interactive Schematic for Use in Analog, Mixed-Signal, and Custom Digital Circuit Design
System and Method for Determining and Visualizing Tradeoffs Between Yield and Performance in Electrical Circuit Designs
Data-Mining-Based Knowledge Extraction and Visualization of Analog/ Mixed-Signal/ Custom Digital Circuit Design Flow
Test Generation Methods for Reducing Power Dissipation and Supply Currents
Timing-Aware Test Generation and Fault Simulation
Conversion of a Three-Dimensional Wire Harness Representative to a Two-Dimensional Orthogonal Wire Harness Representative
Diagnosing Mixed Scan Chain and System Logic Defects
Crosslinking of Netlists
Dram with Word Line Compensation
Defect Localization Based on Defective Cell Diagnosis
Low Power Decompression of Test Cubes
Analysis Optimizer
Built-In Self-Test of Integrated Circuits Using Selectable Weighting of Test Patterns
Model-Based Design Verification
Ram with Trim Capacitors
Memory Row and Column Redundancy
Low-Power Cam Cell
Selective Optical Proximity Layout Design Data Correction
Low Power Scan Testing Techniques and Apparatus
Generating Test Sets for Diagnosing Scan Chain Failures
Methods for Distributing Programs for Generating Test Data
On-The-Fly Improvement of Certainty of Statistical Estimates in Statistical Design, with Corresponding Visual Feedback
Modeling the Skin Effect Using Efficient Conduction Mode Techniques
Forming Separation Directives Using a Printing Feasibility Analysis
Model Based Microdevice Design Layout Correction
Model-Building Optimization
Accurately Identifying Failing Scan Bits in Compression Environments
Segmenting Integrated Circuit Layout Design Files Using Speculative Parsing
Selective Per-Cycle Masking of Scan Chains for System Level Test
Clock Model for Formal Verification of a Digital Circuit Description
Site Selective Optical Proximity Correction
Direct Register Access for Host Simulation
Pre-Bias Optical Proximity Correction
Test Pattern Generation for Diagnosing Scan Chain Failures
Hierarchical Verification Of Clock Domain Crossings
Mask Model Calibration Technologies Involving Etch Effect and Exposure Effect
Electron Beam Simulation Corner Correction for Optical Lithpography
On-Chip Logic To Log Failures During Production Testing And Enable Debugging For Failure Diagnosis
Speed-Path Debug Using at-Speed Scan Test Patterns
Logic Injection
Combination of Ground Devices in Wiring Harness Designs
Random Access Memory for Use in an Emulation Environment
Dual Metric Opc
Selective Shielding for Multiple Exposure Masks
Fault Support in an Emulation Environment
Multi-Mode Multi-Corner Clocktree Synthesis
Modelling and Simulation Method
Resource Remapping in a Hardware Emulation Environment
Identification of Power Sensitive Scan Cells
Related Assignments
(20)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Dec 30, 2003
From: RAYHAWK, JOSEPH C.; DU, XIAOGANG; CHENG, WU-TUNG
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 014882/0756 →
Assignment of Assignor's Interest
Feb 23, 2004
From: SUARIS, PETER R.; LIU, LUNG-TIEN; DING, YUZHENG; CHOU, NAN-CHI
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015025/0487 →
Assignment of Assignor's Interest
Jun 4, 2004
From: MUKHERJEE, NILANJAN; RAYHAWK, JOSEPH C.; KUMAR, AMRENDRA
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015444/0569 →
Assignment of Assignor's Interest
Aug 10, 2004
From: RAJSKI, JANUSZ; WANG, CHEN; MRUGALSKI, GRZEGORZ; TYSZER, JERZY
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015085/0467 →
Assignment of Assignor's Interest
Aug 27, 2004
From: SHEEHAN, BERNARD N.
To: MENTOR GRAPHICS CORP.
Reel/Frame 015741/0326 →
Assignment of Assignor's Interest
Sep 30, 2004
From: KADKADE, SUDHIR DATTARAM
To: LIGHTHOUSE DESIGN AUTOMATION, INC.
Reel/Frame 015868/0527 →
Assignment of Assignor's Interest
Oct 7, 2004
From: RINDERKNECHT, THOMAS HANS; CHENG, WU-TUNG
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015883/0655 →
Assignment of Assignor's Interest
Oct 12, 2004
From: FERGUSON, JOHN G.; PIKUS, FEDOR G.; SAKAJIRI, KYOHEI; GRODD, LAURENCE W.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015238/0864 →
Assignment of Assignor's Interest
Oct 26, 2004
From: HEGAZY, HAZEM MAHMOUD; SAFWAT, AMR M.E.; ABDALLA, WAEL FIKRY FAROUK FIKRY
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015940/0006 →
Assignment of Assignor's Interest
Oct 28, 2004
From: SUARIS, PETER; WANG, DONGSHENG
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015301/0694 →
Assignment of Assignor's Interest
Nov 10, 2004
From: GUTBERLET, PETER PIUS; TAKACH, ANDRES R.; BOWYER, BRYAN DARRELL
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015988/0949 →
Assignment of Assignor's Interest
Dec 21, 2004
From: CHENG, WU-TUNG; HUANG, YU; TSAI, KUN-HAN; RAJSKI, JANUSZ
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015484/0111 →
Assignment of Assignor's Interest
Jan 21, 2005
From: GRANIK, YURI
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016221/0716 →
Assignment of Assignor's Interest
Feb 2, 2005
From: SUAYA, ROBERTO; ESCOVAR, RAFAEL; ORTIZ, SALVADOR
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015647/0162 →
Assignment of Assignor's Interest
Mar 9, 2005
From: RAJSKI, JANUSZ; TANG, HUAXING; WANG, CHEN
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015866/0991 →
Assignment of Assignor's Interest
May 26, 2006
From: ADAMS, LYLE E.
To: PALMCHIP CORPORATION
Reel/Frame 017685/0251 →
Assignment of Assignor's Interest
May 30, 2006
From: PALMCHIP CORPORATION
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 017689/0589 →
Assignment of Assignor's Interest
Jun 1, 2006
From: PALMCHIP CORPORATION
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 017708/0556 →
Assignment of Assignor's Interest
Jul 13, 2006
From: LIGHTHOUSE DESIGN AUTOMATION, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 017929/0722 →
Co-Ownership Agreement
Aug 9, 2006
From: CHIPS & SYSTEMS, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 018090/0350 →