On-chip logic to log failures during production testing and enable debugging for failure diagnosis
View Patent ↗On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature.
1. A method of collecting test data, comprising:
compacting test data to generate a test signature for a test pattern with a compacting device;
transferring the test signature from the compacting device to a debug register, the debug register being cross-coupled with the compacting device;
transferring a compacting device signature from the debug register to the compacting device; and
shifting the test signature out from the debug register.
2. The method recited in claim 1 , wherein:
the compacting device is a multiple input shift/signature (MISR) register.
3. The method recited in claim 1 , wherein:
the test data are obtained by compressing scan chain output data.
4. The method recited in claim 1 , wherein:
the compacting device signature is a fault-free test signature for the test pattern.
5. The method recited in claim 1 , further comprising:
transferring the test signature to comparator circuitry, the comparator circuitry being connected with the debug register; and
generating an output signal based on the test signature with the comparator circuitry.
6. The method recited in claim 5 , wherein:
the comparator circuitry includes a compressor and a comparator, and the comparator receives a compressed fault-free test signature.
7. The method recited in claim 6 , wherein:
the compressed fault-free signature is stored in a read-only memory circuit.
8. A test data collection device, comprising:
a compacting device configured to generate a test signature based on test data; and
a debug register being cross-coupled to the compacting device.
9. The test data collection device recited in claim 8 , further comprising:
comparator circuitry connected to the debug register and configured to generate an output signal based on the test signature and information related to a fault-free signature.
10. The test data collection device recited in claim 9 , wherein:
the comparator circuitry includes a compressor and a comparator, the compressor being connected to the debug register; and
the information related to a fault-free signature is a compressed fault-free signature.
11. The test data collection device recited in claim 8 , wherein:
the compacting device is a multiple input shift/signature (MISR) register.
12. The test data collection device recited in claim 8 , wherein:
the debug register is configured to shift out the test signature received from the compacting device through an output port and to shift in a compacting device signature through an input port.