RAM with trim capacitors
View Patent ↗In one embodiment, a memory is provided that includes: a plurality of memory cells arranged in columns, each column coupled to a corresponding bit line; a sense amplifier adapted to sense the voltage on a pair of the bit lines to determine a binary state of an accessed memory cell coupled to a first one of the bit lines in the pair; and a first trim capacitor having a first terminal directly coupled to one of the bit lines in the pair, the first trim capacitor having an opposing second terminal coupled to a first trim capacitor signal, the memory being adapted to change a voltage of the first trim capacitor signal while the sense amplifier senses the voltage to determine the binary state of the accessed memory cell.
1. A memory, comprising:
a plurality of memory cells arranged in columns, each column coupled to a corresponding bit line;
a sense amplifier adapted to sense the voltage on a pair of the bit lines to determine a binary state of an accessed memory cell coupled to a first one of the bit lines in the pair; and
a first trim capacitor having a first terminal directly coupled to one of the bit lines in the pair, the first trim capacitor having an opposing second terminal coupled to a first trim capacitor signal, the memory being adapted to change a voltage of the first trim capacitor signal while the sense amplifier senses the voltage to determine the binary state of the accessed memory cell.
2. The memory of claim 1 , further comprising: a second trim capacitor having a first terminal directly coupled to a remaining one of the bit lines in the pair, the second trim capacitor having an opposing second terminal coupled to a second trim capacitor signal, the memory being adapted to change a voltage of the second trim capacitor signal while the sense amplifier senses the voltage to determine the binary state of the accessed memory cell.
3. The memory of claim 1 , wherein the memory is adapted to change the voltage of the first trim capacitor signal from a ground state to a power supply voltage VDD.
4. The memory of claim 1 , further comprising: an offset cancellation circuit adapted to cancel an offset bias for the sense amplifier.
5. The memory of claim 1 , wherein the memory is a dynamic random access memory (DRAM).
6. A method of biasing a memory, wherein the memory includes a plurality of memory cells arranged in columns, each column coupled to a corresponding bit line, a sense amplifier adapted to sense the voltage on a pair of the bit lines to determine a binary state of an accessed memory cell coupled to a first one of the bit lines in the pair; and a first trim capacitor having a first terminal directly coupled to one of the bit lines in the pair, the first trim capacitor having an opposing second terminal coupled to a first trim capacitor signal, the method comprising:
writing binary ones and zeroes to the memory cells;
reading the written binary ones and zeroes to determine whether the memory cells favor a binary one bit decision or a binary zero bit decision; and
based upon whether the accessed memory cell favors a binary one bit decision or a binary zero bit decision, driving the first trim capacitor signal while the sense amplifier senses such that the accessed memory cell neither favors a binary one bit decision nor a binary zero bit decision.
7. The method of claim 6 , further comprising: performing the writing and reading acts to determine whether the memory cells favor a binary one bit decision or a binary zero bit decision before a sale of the memory; and burning in a value for the first trim capacitor signal into a non-volatile memory such that the accessed memory cell neither favors a binary one bit decision nor a binary zero bit decision.
8. The method of claim 6 , wherein the memory is a dynamic random access memory (DRAM).