Managing and controlling the use of hardware resources on integrated circuits
View Patent ↗Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed number of hardware resources in a class of hardware resources. One or more operator instances are determined from the RTL description received, where at least some of the operator instances are implementable by the hardware resources in the class of hardware resources. In this embodiment, and prior to initially synthesizing the RTL description into a gate-level netlist, assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources is automatically determined. A graphical user interface is also provided that allows a user to view and modify the assignment information.
1. A method for performing RTL synthesis in a computer-implemented synthesis tool, comprising:
receiving a register-transfer-level (“RTL”) description of a circuit to be implemented in a target architecture, the target architecture having a limited number of hardware resources available in a class of hardware resources;
determining assignment information indicative of how operator instances in the RTL description are to be implemented using the hardware resources in the class of hardware resources; and
displaying to a user one or more of a total number of hardware resources in the class that have been assigned using a user-selected implementation constraint, a total number of hardware resources in the class that have been assigned without using a user-selected implementation constraint, or a total number of hardware resources in the class that are remaining after accounting for current assignments,
wherein the displaying is performed prior to a gate-level netlist being generated according to the assignment information.
2. The method of claim 1 , wherein the class of hardware resources is a first class of hardware resources, the method further comprising,
modifying the assignment information such that at least one of the operator instances is to be implemented using hardware resources in a second class of hardware resources;
calculating how many of the hardware resources in the first class of hardware resources have been assigned after the modification; and
displaying an updated indication of the total number of hardware resources in the first class that are remaining after accounting for current assignments.
3. The method of claim 2 , wherein the modifying is performed in accordance with an implementation constraint selected by the user.
4. The method of claim 1 , further comprising displaying an indication that the hardware resources in the class of hardware resources have been overmapped.
5. The method of claim 1 , wherein the target architecture is one or more field programmable gate arrays (“FPGAs”).
6. The method of claim 1 , wherein the class of hardware resources is one of embedded memory blocks, embedded multiplier blocks, embedded DSP blocks, or logic fabric.
7. One or more computer-readable media storing a gate-level netlist generated by the method of claim 1 .
8. A method for performing RTL synthesis in a computer-implemented synthesis tool, comprising:
receiving a register-transfer-level (“RTL”) description of a circuit to be implemented in a target architecture, wherein the target architecture comprises a fixed number of available hardware resources in a class of hardware resources;
determining one or more operator instances from the RTL description received, at least some of the operator instances being implementable by the hardware resources in the class of hardware resources; and
displaying to a user an indication of the operator instances implementable by the hardware resources in the class of hardware resources.
9. The method of claim 8 , wherein the displaying is performed prior to initially synthesizing the RTL description into a gate-level netlist.
10. The method of claim 8 , further comprising displaying an indication of the number of the hardware resources available in the class of hardware resources.
11. The method of claim 8 , further comprising,
assigning at least one of the operator instances to be implemented using at least one of the hardware resources in the class of hardware resources;
calculating how many of the hardware resources have been assigned; and
displaying an indication of the number of the hardware resources assigned.
12. The method of claim 11 , wherein the assigning is performed in accordance with an implementation constraint selected by the user.
13. The method of claim 11 , further comprising displaying an indication that the hardware resources have been overmapped if the number of the hardware resources assigned exceeds a number of the hardware resources available in the class of hardware resources.
14. The method of claim 8 , further comprising displaying an indication of a number of the hardware resources in the class of hardware resources to which operator instances have not been assigned.
15. The method of claim 8 , wherein the target architecture is one or more field programmable gate arrays (“FPGAs”).
16. One or more computer-readable media storing a gate-level netlist generated by the method of claim 8 .
17. A method for performing synthesis in a register-transfer-level (“RTLD”) synthesis tool, comprising:
receiving an RTL description of a circuit to be implemented in a target architecture;
determining a plurality of operator instances from the RTL description received, the plurality of operator instances being implementable by one or more hardware resources available in the target architecture; and
providing a graphical user interface that displays to a user one or more of the operator instances and allows the user to associate an implementation constraint with at least one of the operator instances, the implementation constraint being selectable from a list of one or more implementation constraints known to be usable for the at least one of the operator instances, and the implementation constraint being indicative of one or more types of hardware resources to be used in implementing the associated at least one of the operator instances.
18. The method of claim 17 , wherein the implementation constraint indicates that an associated operator instance is to be implemented in the target architecture using one of a set of one or more implementation methods, the set of one or more implementation methods consisting of a subset of all implementation methods available for implementing the associated operator instance in the target architecture.
19. The method of claim 17 , further comprising producing a gate-level netlist implementing operator instances in accordance with one or more associated implementation constraints.
20. The method of claim 17 , wherein the graphical user interface displays an associated timing delay or resource usage cost for the implementation constraint.
21. The method of claim 17 , further comprising:
assigning the operator instances to respective hardware resources available in the target architecture; and
displaying in the graphical user interface information about resource usage in the target architecture resulting from the assignment, wherein the displaying is performed before a gate-level netlist is generated from the assignment.
22. The method of claim 21 , wherein the information about resource usage includes one or more of a total number of hardware resources available in the target architecture in a class of hardware resources, a total number of hardware resources in the class that have been assigned using a user-selected implementation constraint, a total number of hardware resources in the class that have been assigned without using a user-selected implementation constraint, or a total number of resources in the class that are remaining after accounting for the assignment.
23. The method of claim 21 , wherein the information about resource usage includes a total number of hardware resources in a class of hardware resources made unavailable for assignment.
24. The method of claim 17 , wherein the target architecture is one or more field programmable gate arrays (“FPGAs”).
25. One or more computer-readable media storing a gate-level netlist generated by the method of claim 17 .
26. A method for performing RTL synthesis in a computer-implemented synthesis tool, comprising:
receiving a register-transfer-level (“RTL”) description of a circuit to be implemented in a target architecture, wherein the target architecture comprises a fixed number of hardware resources in a class of hardware resources;
determining one or more operator instances from the RTL description received, at least some of the operator instances being implementable by the hardware resources in the class of hardware resources; and
prior to initially synthesizing the RTL description into a gate-level netlist, automatically determining assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources and providing a graphical user interface that allows a user to view and modify the assignment information.
27. The method of claim 26 , further comprising displaying in the graphical user interface one or more of a total number of hardware resources available in the target architecture in the class of hardware resources, a total number of hardware resources in the class that have been assigned using a user-selected implementation constraint, a total number of hardware resources in the class that have been automatically assigned without using a user-selected implementation constraint, or a total number of resources in the class that are remaining after accounting for the assignment information.
28. One or more computer-readable media storing a gate-level netlist generated by the method of claim 26 .
29. An RTL synthesis system, comprising:
a computer, wherein the computer is configured to perform a method comprising,
receiving a register-transfer-level (“RTL”) description of a circuit to be
implemented in a target architecture, the target architecture having a limited number of
hardware resources available in a class of hardware resources,
determining assignment information indicative of how operator instances in the
RTL description are to be implemented using the hardware resources in the class of
hardware resources, and
using a graphical user interface, displaying to a user one or more of a total number
of hardware resources in the class that have been assigned using a user-selected
implementation constraint, a total number of hardware resources in the class that have
been assigned without using a user-selected implementation constraint, or a total number
of hardware resources in the class that are remaining after accounting for current
assignments,
wherein the displaying is performed prior to a gate-level netlist being generated
according to the assignment information.
30. The RTL synthesis system of claim 29 , wherein the method further comprises automatically making assignments of operator instances to the hardware resources.
31. The RTL synthesis system of claim 30 , wherein the assignments are based at least in part on heuristics developed from benchmarking experiments with a selected FPGA.
32. The RTL synthesis system of claim 30 , wherein the graphical user interface allows a user to associate an implementation constraint with one or more respective operator instances defined by the RTL description, and wherein the assignments of operator instances to hardware resources are made in accordance with the respective implementation constraints.
33. The RTL synthesis system of claim 29 , wherein, prior to synthesis of the RTL description into the gate-level netlist, the graphical user interface allows the user to modify how at least some of the operators are allocated to the hardware resources and updates the display of how many of the hardware resources remain available to account for the modification.
34. The RTL synthesis system of claim 29 , wherein the graphical user interface allows the user to set a budget for a class of hardware resources that limits how many hardware resources in the class of hardware resources can be assigned to implement operator instances in the RTL description.
35. One or more computer-readable media containing instructions which, when executed by a computer, cause the computer to perform a method for performing synthesis in a register-transfer-level synthesis tool, the method comprising:
receiving a description of a circuit to be implemented in a target architecture;
determining a plurality of arithmetic or datapath operator instances from the description received, the plurality of arithmetic or datapath operator instances being implementable by one or more hardware resources available in the target architecture; and
providing a graphical user interface that displays to a user one or more of the arithmetic or datapath operator instances and allows the user to associate an implementation constraint with at least one of the arithmetic or datapath operator instances, the implementation constraint being selectable from a list of one or more implementation constraints known to be usable for the at least one of the arithmetic or datapath operator instances, and the implementation constraint being indicative of one or more types of hardware resources to be used in implementing the associated at least one of the arithmetic or datapath operator instances.
36. The one or more computer-readable media of claim 35 , the description comprising a register-transfer-level description.
37. The one or more computer-readable media of claim 35 , the description comprising a gate-level netlist with one or more preserved operators.