Branch merge reduction of RLCM networks
View Patent ↗Various tools and techniques are provided for reducing an original circuit network into a simpler, realizable RCLM circuit network. Branches of the original network are merged to reduce its total number of nodes. More particularly, the branches of the original circuit are merged so that the resulting reduced circuit approximately replicates the timing characteristics of the original circuit over the desired operating frequency range. The determination whether to merge two branches is made based upon one or more circuit characteristics associated with the node connecting the branches.
1. A method of approximating operating characteristics of a circuit, comprising:
(1) obtaining a circuit design from a memory;
(2) for each node in the circuit design,
identifying each branch of the node,
determining if the node has only a first incident RL branch and a second incident RL branch,
if the node has only a first incident RL branch and a second incident RL branch, determining if the node and the identified branches of the node meet the criteria of
|τ RC S| being equal to or below a first threshold value, |τ 2 LC s 2 | being equal to or below a second threshold value, |τ 2 M s 2 | being equal to or below a third threshold value, and
R
1
R
1
+
R
2
≈
L
1
-
M
L
1
+
L
2
-
2
M
,
or
|τ RC s| being equal to or below a fourth threshold value, and |τ RL s| being equal to or below a fifth threshold value,
where s is a designated test maximum frequency, R 1 is the resistance of the first incident RL branch, L 1 is the inductance of the first incident RL branch, R 2 is the resistance of the second incident RL branch, L 2 is the inductance of the second incident RL branch, and M is the magnetic coupling between the first incident RL branch and the second incident RL branch, and
where
τ
RL
=
max
{
L
1
-
M
R
1
,
L
2
-
M
R
2
,
M
min
{
R
1
,
R
2
}
}
,
and
where
τ
RC
=
min
{
R
1
,
R
2
}
C
,
and
where
τ
LC
2
=
{
(
L
1
-
M
)
C
if
R
1
<
R
2
(
L
2
-
M
)
C
if
R
2
<
R
1
,
and
where
τ
M
2
=
MC
,
where C is the summation of all capacitors sharing a termination at the node; and
if the node and the identified branches meet either criteria and if it is determined that the node has only a first incident RL branch and a second incident RL branch, merging the identified branches to eliminate the node, and otherwise not merging the identified branches; and
modifying the circuit design to include the merger of the identified branches; and
(3) storing the modified circuit design in a memory.
2. The method recited in claim 1 , wherein at least one of the threshold values is one.
3. The method recited in claim 2 , wherein each of the threshold values is one.
4. The method recited in claim 1 , further comprising repeating step (2) for each of a plurality of different maximum test frequencies.
5. A tangible computer-readable storage medium storing computer-executable instructions that when executed by a processor, perform a method comprising:
(1) obtaining a circuit design from a memory;
(2) for each node in the circuit design,
identifying each branch of the node,
determining if the node has only a first incident RL branch and a second incident RL branch,
if the node has only a first incident RL branch and a second incident RL branch, determining if the node and the identified branches of the node meet the criteria of
|τ RC s| being equal to or below a first threshold value, |τ 2 LC s 2 | being equal to or below a second threshold value, |τ 2 M s 2 | being equal to or below a third threshold value,and
R
1
R
1
+
R
2
≈
L
1
-
M
L
1
+
L
2
-
2
M
,
or
|τ RC s| being equal to or below a fourth threshold value, and |τ RL s| being equal to or below a fifth threshold value,
where s is a designated test maximum frequency, R 1 is the resistance of the first incident RL branch, L 1 is the inductance of the first incident RL branch, R 2 is the resistance of the second incident RL branch, L 2 is the inductance of the second incident RL branch, and M is the magnetic coupling between first incident RL branch and a second incident RL branch, and
where
τ
RL
=
max
{
L
1
-
M
R
1
,
L
2
-
M
R
2
,
M
min
{
R
1
,
R
2
}
}
,
and
where
τ
RC
=
min
{
R
1
,
R
2
}
C
,
and
where
τ
LC
2
=
{
(
L
1
-
M
)
C
if
R
1
<
R
2
(
L
2
-
M
)
C
if
R
2
<
R
1
,
and
where
τ
M
2
=
MC
,
where C is the summation of all capacitors sharing a termination at the node; and
if the node and the identified branches meet either criteria and if it is determined that the node has only a first incident RL branch and a second incident RL branch, merging the identified branches to eliminate the node, and otherwise not merging the identified branches; and
modifying the circuit design to include the merger of the identified branches; and
(3) storing the modified circuit design in a memory.
6. A method of approximating operating characteristics of a circuit, comprising:
(1) obtaining a circuit design from a memory;
(2) for each node in the circuit design,
identifying each branch of the node,
determining if the node has only a first incident RL branch and a second incident RL branch,
responsive to determining that the node fails to have only a first incident RL branch and a second incident RL branch without any other incident RL branches, proceeding to a next node when at least one next node exists that has not been analyzed to determine if the next node has only a first incident RL branch and a second incident RL branch without any other incident RL branches;
responsive to determining that the node has only a first incident RL branch and a second incident RL branch without any other incident RL branches, determining if the node and the identified branches of the node meet the criteria of:
| RC s| being equal to or below a first threshold value, |τ 2 LC s 2 | being equal to or below a second threshold value, |τ 2 M s 2 | being equal to or below a third threshold value, and
R
1
R
1
+
R
2
≈
L
1
-
M
L
1
+
L
2
-
2
M
,
or
|τ RC s| being equal to or below a fourth threshold value, and |τ RL s| being equal to or below a fifth threshold value,
where s is a designated test maximum frequency, R 1 is the resistance of the first incident RL branch, L 1 is the inductance of the first incident RL branch, R 2 is the resistance of the second incident RL branch, L 2 is the inductance of the second incident RL branch, and M is the magnetic coupling between first incident RL branch and a second incident RL branch, and
where
τ
RL
=
max
{
L
1
-
M
R
1
,
L
2
-
M
R
2
,
M
min
{
R
1
,
R
2
}
}
,
and
where
τ
RC
=
min
{
R
1
,
R
2
}
C
,
and
where
τ
LC
2
=
{
(
L
1
-
M
)
C
if
R
1
<
R
2
(
L
2
-
M
)
C
if
R
2
<
R
1
,
and
where
τ
M
2
=
MC
,
where C is the summation of all capacitors sharing a termination at the node; and
if the node and the identified branches meet either criteria and if it is determined that the node has only a first incident RL branch and a second incident RL branch, merging the identified branches to eliminate the node, and otherwise not merging the identified branches; and
modifying the circuit design to include the merger of the identified branches; and
(3) storing the modified circuit design in a memory.
7. The method of claim 1 , wherein the designated test maximum frequency s is applied recursively over multiples of an actual maximum operation frequency.
8. The tangible computer-readable storage medium of claim 5 , wherein the designated test maximum frequency s is applied recursively over multiples of an actual maximum operation frequency.
9. The method of claim 6 , wherein the designated test maximum frequency s is applied recursively over multiples of an actual maximum operation frequency.