Generating test sets for diagnosing scan chain failures
View Patent ↗Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.
1. One or more computer-readable media storing computer-executable instructions for causing a computer to perform a test pattern generation method for a circuit-under-test, the test pattern generation method comprising:
constraining scan-in load values of a targeted scan cell in a scan chain and scan cells in the scan chain downstream of the targeted scan cell to non-fault-activating values;
generating a test pattern that causes a scan cell in the scan chain immediately downstream of the targeted scan cell to capture a fault-activating value during a capture phase of testing, the generating being performed with the scan-in load values of the targeted scan cell of the scan chain and scan cells of the scan chain downstream of the targeted scan cell being constrained to the non-fault-activating values;
storing the test pattern; and
repeating the acts of constraining, generating, and storing for multiple other targeted scan cells in the scan chain.
2. The one or more computer-readable media of claim 1 , wherein the test pattern generation method targets a stuck-at-0 or stuck-at-1 fault in the targeted scan cell.
3. The one or more computer-readable media of claim 1 , wherein the test pattern further causes the targeted scan cell to capture a non-fault activating value during the capture phase of testing.
4. The one or more computer-readable media of claim 3 , wherein the test pattern generation method targets a fast-to-rise fault, fast-to-fall fault, slow-to-rise fault, slow-to-fall fault, fast fault, or slow fault in the targeted scan cell.
5. The one or more computer-readable media of claim 1 , wherein the circuit-under-test comprises decompression hardware for decompressing compressed input stimuli and compression hardware for compacting test responses, and wherein the method further comprises accounting for transformations caused by the decompression hardware and the compression hardware during test pattern generation.
6. One or more computer-readable media storing test patterns generated by a computer executing the instructions stored on the one or more computer-readable media of claim 1 .
7. One or more computer-readable media storing computer-executable instructions for causing a computer to perform a test pattern generation method for a circuit-under-test, the test pattern generation method comprising:
constraining scan-in load values of a targeted scan cell in a scan chain and scan cells in the scan chain downstream of the targeted scan cell to non-fault-activating values, wherein the scan cells downstream of the targeted scan cell are consecutive scan cells, and wherein the first scan cell of the consecutive scan cells begins after the next scan cell downstream of the targeted scan cell;
generating a test pattern that causes the first scan cell to capture a fault-activating value during a capture phase of testing, the generating being performed with the scan-in load values of the targeted scan cell and the scan cells downstream of the targeted scan cell beginning with the first scan cell being constrained to the non-fault-activating values, the generating being further performed with the next scan cell downstream of the targeted scan cell being unconstrained; and
storing the test pattern.
8. The one or more computer-readable media of claim 7 , wherein the test pattern generation method targets a possible stuck-at-0 or stuck-at-1 fault.
9. The one or more computer-readable media of claim 7 , wherein the test pattern further causes a scan cell immediately upstream of the first scan cell to capture a non-fault-activating value during the capture phase of testing.
10. The one or more computer-readable media of claim 9 , wherein the test pattern generation method targets a fast-to-rise fault, fast-to-fall fault, slow-to-rise fault, slow-to-fall fault, fast fault, or slow fault in the targeted scan cell.
11. The one or more computer-readable media of claim 7 , wherein the method further comprises repeating the acts of claim 7 for multiple scan cells in the scan chain.
12. The one or more computer-readable media of claim 7 , wherein the circuit-under-test comprises decompression hardware for decompressing compressed input stimuli and compression hardware for compacting test responses, and wherein the method further comprises accounting for transformations caused by the decompression hardware and the compression hardware during test pattern generation.
13. A method of test pattern generation for a circuit-under-test, comprising:
constraining scan-in load values of a targeted scan cell in a scan chain and scan cells in the scan chain downstream of the targeted scan cell to non-fault-activating values;
generating a test pattern that causes a scan cell in the scan chain immediately downstream of the targeted scan cell to capture a fault-activating value during a capture phase of testing, the generating being performed with the scan-in load values of the targeted scan cell in the scan chain and the scan cells in the scan chain downstream of the targeted scan cell being constrained to the non-fault-activating values;
storing the test pattern; and
repeating the acts of constraining, generating, and storing for multiple other targeted scan cells in the scan chain.
14. The method of claim 13 , wherein the test pattern generation method targets a stuck-at-0 or stuck-at-1 fault in the targeted scan cell.
15. The method of claim 13 , wherein the test pattern further causes the targeted scan cell to capture a non-fault-activating value during the capture phase of testing.
16. The method of claim 15 , wherein the test pattern generation method targets a fast-to-rise fault, fast-to-fall fault, slow-to-rise fault, slow-to-fall fault, fast fault, or slow fault in the targeted scan cell.
17. The method of claim 13 , wherein the circuit-under-test comprises decompression hardware for decompressing compressed input stimuli and compression hardware for compacting test responses, and wherein the method further comprises accounting for transformations caused by the decompression hardware and the compression hardware during test pattern generation.
18. A method of test pattern generation for a circuit-under-test, comprising:
constraining scan-in load values of a targeted scan cell in a scan chain and scan cells in the scan chain downstream of the targeted scan cell to non-fault-activating values, wherein the scan cells downstream of the targeted scan cell are consecutive scan cells, and wherein the first scan cell of the consecutive scan cells begins after the next scan cell downstream of the targeted scan cell;
generating a test pattern that causes the first scan cell to capture a fault-activating value during a capture phase of testing, the generating being performed with the scan-in load values of the targeted scan cell and the scan cells downstream of the targeted scan cell beginning with the first scan cell being constrained to the non-fault-activating values, the generating being further performed with the next scan cell downstream of the targeted scan cell being unconstrained; and
storing the test pattern.
19. The method of claim 18 , wherein the test pattern generation method targets a possible stuck-at-0 or stuck-at-1 fault.
20. The method of claim 18 , wherein the test pattern further causes a scan cell immediately upstream of the first scan cell to capture a non-fault-activating value during the capture phase of testing.
21. The method of claim 20 , wherein the test pattern generation method targets a fast-to-rise fault, fast-to-fall fault, slow-to-rise fault, slow-to-fall fault, fast fault, or slow fault in the targeted scan cell.
22. The method of claim 18 , wherein the method further comprises repeating the acts of claim 7 for multiple scan cells in the scan chain.
23. The method of claim 18 , wherein the circuit-under-test comprises decompression hardware for decompressing compressed input stimuli and compression hardware for compacting test responses, and wherein the method further comprises accounting for transformations caused by the decompression hardware and the compression hardware during test pattern generation.