Memory row and column redundancy
View Patent ↗In one embodiment, a memory includes a row and/or column redundancy architecture that uses binary cells to indicate whether a given row or column of memory cells is faulty. The binary cell is adapted to store a “repair true” signal in response to a conventional access to the corresponding row or column and also the assertion of a set signal.
1. A memory, comprising:
a redundant row-unit having one or more rows of memory cells;
a plurality of memory cells arranged according to rows, wherein the rows are arranged into a plurality of row-units such that each row-unit has the same number of rows, and wherein the redundant row-unit includes the same number of rows;
a plurality of SRAM repair cells corresponding on a one-to-one basis with the plurality of row-units, each SRAM repair cell operable to store a repair true or false value signal, and wherein each SRAM repair cell is adapted to store a repair false signal in response to an assertion of a reset signal; and
an X decoder for addressing the rows, the X decoder adapted to respond to an address for a row-unit having a repair memory cell storing the repair true signal by addressing a unit selected from the remaining row-units and the redundant row-unit, wherein each SRAM repair memory cell is adapted to store the repair true signal in response to an assertion of a set signal and an addressing of the corresponding row-unit.
2. The memory of claim 1 , wherein the memory is incorporated in an integrated circuit, the integrated circuit including a pin for receiving the reset signal and a pin for receiving the set signal.
3. The memory of claim 1 , wherein the memory is adapted such that each SRAM repair cell stores a repair true signal in response to the assertion of the set signal and an assertion of a wordline within the corresponding row-unit.
4. The memory of claim 3 , wherein the memory is adapted such that the assertion of the wordline corresponds to a read operation.
5. The memory of claim 3 , wherein the memory is adapted such that the assertion of the wordline corresponds to a write operation.
6. The memory of claim 1 , wherein each SRAM repair cell comprises a flip-flop.
7. The memory of claim 6 , wherein each row-unit includes an OR gate adapted to logically OR the row-unit's wordlines to form a wordline signal, and wherein each flip-flop has an asynchronous set input responsive to a logical AND of the set signal and the wordline signal.
8. The memory of claim 7 , wherein each flip-flop has a D input tied to ground and a clock input tied to the set signal, whereby each flip-flop may be reset to store a repair false signal without requiring an external reset signal.
9. A memory, comprising:
a redundant column-unit having one or more columns of memory cells;
a plurality of memory cells arranged according to columns, wherein the columns are arranged into a plurality of column-units such that each column-unit has the same number of columns, and wherein the redundant column-unit includes the same number of columns;
a plurality of SRAM repair cells corresponding on a one-to-one basis with the plurality of column-units, each SRAM repair cell operable to store a repair true or false value signal, wherein each SRAM repair cell is adapted to store a repair false signal in response to an assertion of a reset signal; and
an Y driver for driving the columns, the Y driver adapted to respond to an access for a column-unit having a repair memory cell storing the repair true signal by accessing a unit selected from the remaining column units and the redundant column-unit, wherein each repair memory cell is adapted to store the repair true signal in response to an assertion of a set signal and a write operation for the corresponding column-unit.
10. The memory of claim 9 , wherein the memory is incorporated in an integrated circuit, the integrated circuit including a pin for receiving the reset signal and a pin for receiving the set signal.
11. The memory of claim 9 , wherein each SRAM repair cell comprises a flip-flop.
12. The memory of claim 11 , wherein each column-unit includes an OR gate adapted to logically OR the column-unit's bitlines to form a bitline signal, and wherein each flip-flop has an asynchronous set input responsive to a logical AND of the set signal and the bitline signal.
13. The memory of claim 12 , wherein each flip-flop has a D input tied to ground and a clock input tied to the set signal, whereby each flip-flop may be reset to store a repair false signal without requiring an external reset signal.