Accurately identifying failing scan bits in compression environments
View Patent ↗X-masking registers are added in front of a compactor in test data compression environment to remove unknown values. The X-masking registers block out some chains due to unknown values and select other chains to feed the compactor. This X-masking capability is used to select one scan cell to observe at a time after a failure is observed at the compactor output.
1. An integrated circuit device, comprising:
functional circuitry;
a plurality of scan chains configured to capture test responses from the functional circuitry and to scan out the test responses;
a masking circuit configured to block one or more scan chains selected from the plurality of scan chains to mask the test responses, the masking circuit comprising a register that can be converted to, in response to detecting failing data, a linear feedback state machine for selecting the one or more scan chains, the linear feedback state machine comprising one or more exclusive OR gates; and
a compactor configured to compact the masked test responses received from the masking circuit.
2. The integrated circuit device of claim 1 , wherein the linear feedback state machine is implemented using a modified shift register.
3. The integrated circuit device of claim 1 , wherein the linear feedback state machine is implemented using a modified hold register.
4. The integrated circuit device of claim 1 , further comprising a bit select module configured to enable the masking circuit to work in a bit select mode.
5. The integrated circuit device of claim 1 , further comprising a detection circuit configured to detect failing data from the test responses and to trigger a bit select mode when the failing data is detected.
6. A method of debugging in a test compression environment, the method comprising:
monitoring test responses while the test responses are scanning out and compressed; and
switching to a bit select mode in response to detecting failing data in the test responses, wherein the bit select mode comprises:
changing a shift register or a hold register in a masking circuit to work as a linear feedback state machine, the linear feedback state machine comprising one or more exclusive OR gates.
7. The method recited in claim 6 , wherein the bit select mode further comprises stopping scanning out the test responses.