Hierarchical verification of clock domain crossings
View Patent ↗The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verification interface files are generated by the block level clock domain crossing process. After which, a top level clock domain crossing verification process is performed over the entire design. In various implementations, the top level clock domain crossing verification process utilizes the verification interface files to verify clock domain crossing signals between blocks. Additionally, in some implementations, blocks not verified during block level verification are verified during top level verification. With some implementations of the invention, the device design is partitioned based input from a user of the implementation. Furthermore, in various implementations, the specific clock domain crossing verification checks employed during block level verification and top level verification are specified by a user of the implementation.
1. A method for performing hierarchical verification of a device design comprising:
accessing a device design having a plurality of hardware blocks;
designating hardware blocks of the plurality of hardware blocks having more than one clock domain for a clock domain crossing verification;
forming a block-level group from designated hardware blocks;
employing a the computer to perform a block-level clock domain crossing verification process on the block-level group, the block-level clock domain crossing verification process generating a plurality of block-level interface models;
employing the computer to perform a top-level clock domain crossing verification process to be performed on the device design based in part upon the block-level interface models; and
saving results of the top-level clock domain crossing verification process to a memory storage location.
2. The method of claim 1 , wherein: (a) the designated hardware blocks of the plurality of hardware blocks are divided into a first plurality of designated hardware blocks and a second plurality of designated hardware blocks, (b) the block-level group is formed from the first plurality of designated hardware blocks, and (c) forming the block-level group includes forming a top-level group from the second plurality of designated hardware blocks.
3. The method of claim 1 , wherein employing the computer to perform a block-level clock domain crossing verification process includes performing a clock domain crossing verification process on each hardware block of the block-level group.
4. The method of claim 1 , further comprising saving results of the block-level clock domain crossing verification process to a memory storage location.
5. The method of claim 1 , further comprising saving each of the plurality of block-level interface models to a memory storage location as a block-level interface modeling file.
6. The method of claim 1 , wherein one or more of the plurality of block-level interface models specifies a plurality of clock ports.
7. The method of claim 1 , wherein one or more of the plurality of block-level interface models specifies a plurality of ports that are within the same clock domain.
8. The method of claim 1 , wherein one or more of the plurality of block-level interface models specifies an output port having a pure combinational path to an input port.
9. The method of claim 1 , wherein one or more of the plurality of block-level interface models specifies at least one of: (a) an input port having combinational logic on its fan-out, and (b) an output port having combinational logic on its fan-in.
10. The method of claim 1 , wherein one or more of the plurality of block-level interface models specifies a sampling clock for an input port.
11. A method for performing hierarchical clock domain crossing verification using a computer system, the method comprising:
using the computer system to access a device design having block-level group of design blocks and a top-level group of design blocks, each of the block-level group and the top-level group including a plurality of asynchronous clocks;
initiating a first clock domain crossing verification process for one or more design blocks of the block-level group to generate interface modeling information;
initiating a second clock domain crossing verification process for the top-level group utilizing the interface modeling information to verify one or more clock domain crossings between the block-level group and the top-level group; and
reporting one or more clock domain crossing violations.
12. The method of claim 11 , wherein initiating the first clock domain crossing verification process includes initiating a clock domain crossing verification process for each design block of the block-level group.
13. The method of claim 11 , further comprising saving the interface modeling information to a memory storage location as one or more interface modeling files.
14. The method of claim 11 , further comprising modifying one or more interface modeling files to include the interface modeling information.
15. The method of claim 11 , further comprising saving, to a memory storage location, the results of at least one of: (a) the first clock domain crossing verification process initiated for the one or more design blocks of the block-level group, and (b) the second clock domain crossing verification process initiated for the top-level group.
16. A method for performing hierarchical clock domain crossing verification using a computer system, the method comprising:
using the computer system to access a device design having a top-level, a plurality of design blocks, and a plurality of asynchronous clocks;
dividing the device design into a partitioned device design having a block-level group including one or more first design blocks of the plurality of design blocks and a top-level group including one or more second design blocks of the plurality of design blocks;
performing a first clock domain crossing verification process on each design block of the one or more first design blocks to generate interface modeling information corresponding with each design block;
performing a second clock domain crossing verification process on the top-level, each of the first design blocks being represented by the corresponding interface modeling information; and
reporting one or more clock domain crossing violations.
17. The method of claim 16 , further comprising saving the interface modeling information to a memory storage location as one or more interface modeling files.
18. The method of claim 16 , further comprising modifying one or more interface modeling files to include the interface modeling information.
19. The method of claim 16 , further comprising saving, to a memory storage location, the results of at least one of: (a) performing the first clock domain crossing verification process on each design block of the one or more first design blocks, and (b) performing the second clock domain crossing verification process on the top-level.