Flat panel display and method for fabricating the same
View Patent ↗A flat panel display, having an anti-electrostatic configuration, comprising a plurality of gate lines and data lines formed on an insulating substrate having an emission region and a pad portion, an anti-electrostatic wire initially coupling the gate lines, and an anti-electrostatic circuit coupled to a data line. The anti-electrostatic wire between a gate line and an adjacent gate line is subsequently cut by an opening for cutting the anti-electrostatic wire to electrically isolate the respective gate lines.
1. A flat panel display, comprising:
a plurality of gate lines and a plurality of data lines formed on a substrate;
an anti-electrostatic wire comprising a first portion and a second portion formed between a gate line and an adjacent gate line;
an interlayer insulating layer formed on the anti-electrostatic wire and the gate lines;
a source electrode and a drain electrode formed on the interlayer insulting layer;
a passivation layer formed on the source electrode and the drain electrode;
an anti-electrostatic circuit coupled to a data line, and formed on the interlayer insulating layer; and
a gate insulating layer formed on the substrate, the gate lines and the anti-electrostatic wire being formed on the gate insulating layer,
wherein the interlayer insulating layer has an opening, the opening corresponding to a gap separating the first portion of the anti-electrostatic wire from the second portion of the anti-electrostatic wire,
wherein the passivation layer fills the gap between the first portion and the second portion of the anti-electrostatic wire, and
wherein the passivation layer contacts the source electrode, the drain electrode, and the gate insulating layer.
2. The flat panel display of claim 1 , wherein the anti-electrostatic wire is formed in a region of the substrate between an emission region and a pad portion.
3. The flat panel display of claim 1 , wherein the anti-electrostatic wire comprises at least two lines in parallel with each other, each of the at least two lines comprising the first portion and the second portion.
4. The flat panel display of claim 3 , wherein the anti-electrostatic wire and the gate lines are both disposed directly on the same layer.
5. The flat panel display of claim 4 , wherein the at least two lines are disposed between the gate line and the adjacent gate line.
6. The flat panel display of claim 3 , wherein the at least two lines are disposed between the gate line and the adjacent gate line.
7. The flat panel display of claim 1 , wherein the opening is wider than the anti-electrostatic wire.
8. The flat panel display of claim 1 , wherein the anti-electrostatic wire further comprises a third portion between the gate line and the adjacent gate line, and the interlayer insulating layer has a first opening corresponding to the gap separating the first portion of the anti-electrostatic wire from the second portion of the anti-electrostatic wire and a second opening corresponding to a gap separating the second portion of the anti-electrostatic wire from the third portion of the anti-electrostatic wire.
9. The flat panel display of claim 8 , wherein the anti-electrostatic wire and the gate lines are both disposed directly on the same layer.
10. The flat panel display of claim 1 , wherein the anti-electrostatic wire and the gate lines are both disposed directly on the same layer.
11. The flat panel display of claim 1 , wherein the anti-electrostatic wire and the gates lines are formed of the same layer.
12. The flat panel display of claim 1 , wherein the passivation layer contacts the gate insulating layer via the opening of the interlayer insulating layer.