Power line communication using power factor correction circuits
A PFC circuit modulating a power line using pulse width modulation (PWM) to drive a power MOSFET and series inductor across the power line. Since many modern electronic systems include a power factor correction circuit (PFC) that already includes a series inductor and power MOSFET, a PLC is incorporated into a controller to inject a PLC transmit signal into a control loop for the PFC circuit. This can be done using either an analog PFC controller, such as the UCC28517, the UCC2819A, or a digital PFC controller such as based on a TMS320C24xx DSP.
1. A power factor correction (PFC) circuit, comprising:
a pulse width modulator (PWM) providing a PWM control signal;
a power MOSFET adapted to control a line current drawn from a power line based on the PWM control signal; and
wherein the PWM control signal is constructed so that both a 50 Hz and 60 Hz said line current is controlled to maintain a desired power factor and a higher frequency current is applied to the power line to implement the transmission of a Power Line Communications (PLC) waveform.
2. The power factor correction circuit as specified in claim 1 wherein the PLC waveform has a plurality of subcarriers having subcarrier frequencies, and the subcarrier frequencies are defined so that there is no overlapping of frequency content due to the modulation of the PLC waveform with the 50 Hz and 60 Hz line voltage.
3. The power factor correction circuit as specified in claim 2 wherein the PLC carrier frequency contains information from multiple output bins of a IFFT/FFT algorithm each having a different subcarrier frequency.
4. The power factor correction circuit as specified in claim 3 wherein the subcarrier frequencies are modulated using binary phase shift keying (BPSK).
5. The power factor correction circuit as specified in claim 3 wherein the subcarrier frequencies are spaced 30 Hz apart for the 60 Hz line current, and 25 Hz apart for the 50 Hz line current, and the subcarriers are grouped into blocks of 4 so that each received subcarrier contains information from only one message bit.
6. The power factor correction circuit as specified in claim 3 wherein the subcarrier frequencies are spaced 60 Hz apart for the 60 Hz line current, and 50 Hz apart for the 50 Hz line current and the subcarriers are grouped into blocks of 2 so that each received subcarrier contains information from only one message bit.
7. The power factor correction circuit as specified in claim 3 wherein the PWM has a signal processing sample rate of 7680 Hz for the 60 Hz line current, and 6400 Hz for the 50 Hz line current, and the IFFT/FFT algorithm has a frame length of 256 samples and the subcarrier frequency spacing is 30 Hz for the 60 Hz line current and 25 Hz for the 50 Hz line current.
8. The power factor correction circuit as specified in claim 3 wherein the PWM has a signal processing sample rate of 7680 Hz for a 60 Hz line current, and 6400 Hz for the 50 Hz line current and the IFFT/FFT algorithm has a frame length of 128 samples and the subcarrier frequency spacing is 60 Hz for the 60 Hz line current and 25 Hz for the 50 Hz line current.