IP Library Granted Patent US 8,036,873
Granted Patent B2
US 8,036,873 · App. 11/069,616 · Granted Oct 11, 2011

Efficient clock models and their use in simulation

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Quick Facts
Patent No.
US 8,036,873
App. No.
11/069,616
Granted
Oct 11, 2011
Kind
B2
Abstract

Methods simulating a system of devices are described. A model that simulates the system is executed. The system model includes a plurality of modules. A clock object for a module can be disabled when it is not needed or not being used.

Claims (32)

1. A computer-implemented method of simulating a system of devices, said method comprising:

executing a system model comprising a plurality of software modules including a first module representing a first device of said devices and a second module representing a second device of said devices, wherein a first software clock object is associated with said first module and a second software clock object is associated with said second module and wherein said second software clock object advances fewer clock cycles per unit of time during a simulation relative to said first software clock object, said simulation performed using said system model;

during said simulation, monitoring said first module to determine if said first module is active and monitoring said second module to determine if said second module is active; and

during said simulation, using said second software clock object to drive both said first and second modules when both said first and second modules are active, using said second software clock object to drive said second module when said second module is active but said first module is inactive, and disabling said second software clock object and using said first software clock object to drive said first module when said first module is active but said second module is inactive.

2. The method of claim 1 further comprising monitoring processes in said simulation that are sensitive to said second software clock object, wherein said second software clock object is disabled when no processes are sensitive to said second software clock object.

3. The method of claim 1 further comprising receiving an indication that a process in said simulation that is sensitive to said second software clock object is no longer sensitive to said second software clock object.

4. The method of claim 1 further comprising enabling said second software clock object for said second module in response to said second module becoming active.

5. The method of claim 1 further comprising receiving an indication that a process in said simulation is waiting for a clock event from said second software clock object.

6. The method of claim 1 wherein said system model is constructed in a language substantially compliant with SystemC and comprises statically-sensitive processes and dynamically-sensitive processes.

7. The method of claim 6 further comprising maintaining a count of statically-sensitive processes, wherein said second software clock object is disabled when said count is zero and no dynamically-sensitive processes are sensitive to said second software clock object.

8. A computer-usable non-transitory medium having computer-readable program code embodied therein for causing a computer system to execute a method for simulating a system of devices, said method comprising:

executing a system model comprising a plurality of software modules including a first module representing a first device of said devices and a second module representing a second device of said devices, wherein a first software clock object is associated with said first module and a second software clock object is associated with said second module, and wherein said second software clock object advances fewer clock cycles per simulation unit of time during a simulation relative to said first software clock object, said simulation performed using said system model;

during said simulation, monitoring said first module to determine if said first module is active and monitoring said second module to determine if said second module is active; and

during said simulation, using said second software clock object to drive both said first and second modules when both said first and second modules are active, using said second software clock object to drive said second module when said second module is active but said first module is inactive, and disabling said second software clock object and using said first software clock object to drive said first module when said first module is active but said second module is inactive.

9. The computer-usable non-transitory medium of claim 8 wherein said method further comprises monitoring processes in said simulation that are sensitive to said second software clock object, wherein said second software clock object is disabled when no processes are sensitive to said second software clock object.

10. The computer-usable non-transitory medium of claim 8 wherein said method further comprises receiving an indication that a process in said simulation that is sensitive to said second software clock object is no longer sensitive to said second software clock object.

11. The computer-usable non-transitory medium of claim 8 wherein said method further comprises enabling said second software clock object for said second module in response to said second module becoming active.

12. The computer-usable non-transitory medium of claim 8 wherein said method further comprises receiving an indication that a process in said simulation is waiting for a clock event from said second software clock object.

13. The computer-usable non-transitory medium of claim 8 wherein said system model is constructed in a language substantially compliant with SystemC and comprises statically-sensitive processes and dynamically-sensitive processes.

14. The computer-usable non-transitory medium of claim 13 wherein said second clock object maintains a count of statically-sensitive processes, wherein said second software clock object is disabled when said count is zero and no dynamically-sensitive processes are sensitive to said second software clock object.

15. A computer system comprising:

a processor; and

a memory unit coupled to said processor, said memory unit containing instructions that when executed implement a computer-implemented method for simulating a system of devices, said method comprising:

executing a system model comprising a plurality of software modules including a first module representing a first device of said devices and a second module representing a second device of said devices, wherein a first software clock object is associated with said first module and a second software clock object is associated with said second module and wherein said second software clock object advances fewer clock cycles per unit of simulation time during a simulation relative to said first software clock object, said simulation performed using said system model;

during said simulation, monitoring said first module to determine if said first module is active and monitoring said second module to determine if said second module is active; and

during said simulation, using said second software clock object to drive both said first and second modules when both said first and second modules are active, using said second software clock object to drive said second module when said second module is active but said first module is inactive, and disabling said second software clock object and using said first software clock object to drive said first module when said first module is active but said second module is inactive.

16. The computer system of claim 15 wherein said method further comprises monitoring processes in said simulation that are sensitive to said second software clock object, wherein said second software clock object is disabled when no processes are sensitive to said second software clock object.

17. The computer system of claim 15 wherein said method further comprises receiving an indication that a process in said simulation that is sensitive to said second software clock object is no longer sensitive to said second software clock object.

18. The computer system of claim 15 wherein said method further comprises enabling said second software clock object for said second module in response to said second module becoming active.

19. The computer system of claim 15 wherein said method further comprises receiving an indication that a process in said simulation is waiting for a clock event from said second software clock object.

20. The computer system of claim 15 wherein said system model is constructed in a language substantially compliant with SystemC and comprises statically-sensitive processes and dynamically-sensitive processes.

21. The computer system of claim 20 wherein said second clock object maintains a count of statically-sensitive processes, wherein said second software clock object is disabled when said count is zero and no dynamically-sensitive processes are sensitive to said second software clock object.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2011
From: COWARE, LLC
To: SYNOPSYS, INC.
Reel/Frame 025754/0505 →
CHANGE OF NAME Recorded Jan 26, 2011
From: COWARE, INC.
To: COWARE, LLC
Reel/Frame 025703/0401 →
SECURITY AGREEMENT Recorded Jan 2, 2008
From: COWARE, INC.
To: SILICON VALLEY BANK
Reel/Frame 020308/0157 →
SECURITY AGREEMENT Recorded Jan 2, 2008
From: COWARE, INC.
To: GOLD HILL VENTURE LENDING 03, L.P.; SILICON VALLEY BANK
Reel/Frame 020308/0236 →
CORRECTIVE ASSIGNMENT TO CORRECT NAME OF INVENTOR KARL Recorded Aug 4, 2006
From: VERMEERSCH, DIRK; VAN ROMPAY, KARL
To: COWARE, INC.
Reel/Frame 018147/0200 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2005
From: VERMEERSCH, DIRK; ROMPAY, KARL VAN
To: COWARE, INC.
Reel/Frame 016646/0127 →