IP Library › Assignment 025703/0401
Patent Assignment
Reel/Frame 025703/0401

Change of Name

Recorded: 2011-01-26 Pages: 7
Assignor
COWARE, INC.
Executed: 2010-03-23
Assignee
COWARE, LLC
700 EAST MIDDLEFIELD ROAD, MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Properties (51)
Method and System for Instruction-Set Architecture Simulation Using Just in Time Compilation
Patent: 8,086,438 →
Application: 10/309,554 →
Publication: US 2003/0217248
Automatic Generation of Structure and Control Path Using Hardware Description Language
Patent: 7,373,638 →
Application: 10/641,457 →
Method of Protocol Conversion Between Synchronous Protocols That Are Suitable for Synthesis
Patent: 7,512,732 →
Application: 10/700,600 →
Automatic Generation of Transaction Level Bus Simulation Instructions from Bus Protocol
Patent: 8,090,564 →
Application: 10/700,601 →
Generation of compiler description from architecture description
Patent: 8,677,312 →
Application: 10/815,228 →
Resource Management in a Multicore Architecture
Patent: 8,533,716 →
Application: 10/816,328 →
Publication: US 2005/0223382
Generation of instruction set from architecture description
Patent: 8,595,688 →
Application: 10/936,230 →
Determining Large-Scale Finite State Machines Using Constraint Relaxation
Patent: 8,265,920 →
Application: 10/937,068 →
Large Scale Finite State Machines
Patent: 7,783,997 →
Application: 10/937,645 →
Debug in a Multicore Architecture
Patent: 9,038,070 →
Application: 10/941,457 →
Publication: US 2006/0069953
Transaction Level Model Synthesis
Patent: 8,413,106 →
Application: 10/976,402 →
Interface Converter for Unified View of Multiple Computer System Simulations
Patent: 7,716,031 →
Application: 11/066,841 →
Publication: US 2006/0195821
Method and System for Dynamically Adjusting Speed Versus Accuracy of Computer Platform Simulation
Patent: 7,742,905 →
Application: 11/066,945 →
Publication: US 2006/0195825
Processor/Memory Co-Exploration at Multiple Abstraction Levels
Patent: 7,788,078 →
Application: 11/069,496 →
Efficient Clock Models and Their Use in Simulation
Patent: 8,036,873 →
Application: 11/069,616 →
Publication: US 2006/0195310
Scheduling of Instructions
Patent: 8,689,202 →
Application: 11/096,184 →
Method and Device for Simulator Generation Based on Semantic to Behavioral Translation
Patent: 7,313,773 →
Application: 11/139,373 →
Compiler Retargeting Based on Instruction Semantic Models
Patent: 9,280,326 →
Application: 11/140,353 →
Method and System for Automatic Generation of Instruction-Set Documentation from an Abstract Processor Model Described Using a Hierarchical Architectural Description Language
Patent: 8,006,225 →
Application: 11/145,240 →
Scalable Language Infrastructure for Electronic System Level Tools
Patent: 8,104,016 →
Application: 11/356,578 →
Publication: US 2007/0150851
User interface for facilitation of high level generation of processor extensions
Patent: 9,064,076 →
Application: 11/388,484 →
Scheduling in a multicore processor
Patent: 8,732,439 →
Application: 11/540,146 →
Publication: US 2007/0220517
Managing Power Consumption in a Multicore Processor
Patent: 8,533,503 →
Application: 11/541,315 →
Publication: US 2007/0220294
Dynamic host code generation from architecture description for fast simulation
Patent: 9,830,174 →
Application: 11/584,402 →
Publication: US 2007/0150873
Techniques for Creating and Using a Hierarchical Data Structure
Patent: 9,697,211 →
Application: 11/607,243 →
System and method for stopping integrated circuit simulation
Patent: 9,317,636 →
Application: 11/637,374 →
Techniques for Coordinating and Controlling Debuggers in a Simulation Environment
Patent: 8,423,959 →
Application: 11/637,376 →
Method and system for instruction set simulation with concurrent attachment of multiple debuggers
Patent: 8,914,274 →
Application: 11/637,418 →
Simulation with Dynamic Run-Time Accuracy Adjustment
Patent: 8,543,367 →
Application: 11/707,412 →
Run-Time Switching for Simulation with Dynamic Run-Time Accuracy Adjustment
Patent: 7,899,661 →
Application: 11/707,413 →
Publication: US 2007/0192079
Caching Information to Map Simulation Addresses to Host Addresses in Computer System Simulations
Patent: 7,881,921 →
Application: 11/824,880 →
System and Method of Debugging Multi-Threaded Processes
Patent: 8,683,444 →
Application: 12/001,238 →
Simulation Control Techniques
Patent: 8,397,220 →
Application: 12/030,192 →
Interface Converter for Unified View of Multiple Computer System Simulations
Patent: 8,793,115 →
Application: 12/777,526 →
Publication: US 2011/0119043
Method for Dynamically Adjusting Speed Versus Accuracy of Computer Platform Simulation
Patent: 8,484,006 →
Application: 12/819,981 →
Publication: US 2011/0035201
Large Scale Finite State Machines
Patent: 8,448,106 →
Application: 12/840,211 →
Techniques for Processor/Memory Co-Exploration at Multiple Abstraction Levels
Patent: 8,285,535 →
Application: 12/871,884 →
Publication: US 2010/0324880
Universal technique for fast and flexible instruction-set architecture simulation
Application: 60/368,439 →
Architecture implementation using the machine description language LISA
Application: 60/403,882 →
Methodology for automatic encoding synthesis using hierarchical processor models
Application: 60/501,475 →
Processor/memory co-exploration on multiple abstraction levels
Application: 60/548,711 →
Method and system of scheduling instructions
Application: 60/558,334 →
C compiler retargeting based on instruction semantics models
Application: 60/574,794 →
Automatic extraction of compiler rule patterns from hierarchical architecture description languages
Application: 60/577,163 →
Large-scale finite state machines
Application: 60/592,650 →
Scalable language infrastructure for electronic system level tools
Application: 60/753,899 →
Scalable language infrastructure for ESL tools
Application: 60/753,934 →
Virtual embedded software performance estimation
Application: 60/774,947 →
Techniques for optimizing the memory path in whole system simulations
Application: 60/818,820 →
System and method for enhanced debugging of virtual platforms
Application: 60/874,436 →
Simulation Control Techniques
Application: 60/889,523 →
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jan 5, 2004
From: SCHLIEBUSCH, OLIVER; HOFFMANN, ANDREAS; NOHL, ACHIM; BRAUN, GUNNAR
To: COWARE INC.
Reel/Frame 014848/0532 →
Assignment of Assignor's Interest Mar 22, 2004
From: MICHIELS, TOM; VAN ROMPAEY, KARL
To: COWARE, INC.
Reel/Frame 015119/0196 →
Assignment of Assignor's Interest Mar 31, 2004
From: BRAUN, GUNNAR; HOFFMANN, ANDREAS; GREIVE, VOLKER
To: COWARE, INC.
Reel/Frame 015180/0368 →
Assignment of Assignor's Interest Apr 19, 2004
From: GOOSSENS, SERGE
To: COWARE, INC.
Reel/Frame 015226/0466 →
Assignment of Assignor's Interest Jul 1, 2004
From: LIPPETT, MARK DAVID
To: IGNIOS LIMITED
Reel/Frame 015525/0358 →
Assignment of Assignor's Interest Sep 8, 2004
From: VANSPAUWEN, NIELS
To: COWARE, INC.
Reel/Frame 015784/0104 →
Assignment of Assignor's Interest Sep 8, 2004
From: VANSPAUWEN, NIELS
To: COWARE INC.
Reel/Frame 015791/0658 →
Assignment of Assignor's Interest Oct 28, 2004
From: GOOSSENS, SERGE
To: COWARE, INC.
Reel/Frame 015943/0028 →
Security Agreement Jan 3, 2005
From: COWARE, INC.
To: VENTURE LENDING & LEASING IV, INC.
Reel/Frame 016116/0011 →
Assignment of Assignor's Interest Jan 6, 2005
From: LIPPETT, MARK DAVID; OUNG, AYEWIN
To: IGNIOS LIMITED
Reel/Frame 016125/0414 →
Assignment of Assignor's Interest Mar 30, 2005
From: BRAUN, GUNNAR; HOFFMANN, ANDREAS; GREIVE, VOLKER; HOHENAUER, MANUEL
To: COWARE, INC.
Reel/Frame 016442/0958 →
Assignment of Assignor's Interest Apr 1, 2005
From: GRIEVE,VOLKER; NOHL, ACHIM
To: COWARE, INC.
Reel/Frame 016415/0440 →
Assignment of Assignor's Interest Jun 3, 2005
From: VERMEERSCH, DIRK; ROMPAY, KARL VAN
To: COWARE, INC.
Reel/Frame 016646/0127 →
Assignment of Assignor's Interest Jun 3, 2005
From: VANSPAUWEN, NIELS; MICHIELS, TOM; VAN ROMPAEY, KARL
To: COWARE, INC.
Reel/Frame 016646/0076 →
Assignment of Assignor's Interest Jun 6, 2005
From: VANSPAUWEN, NIELS; MICHIELS, TOM; VAN ROMPAEY, KARL
To: COWARE, INC.
Reel/Frame 016654/0197 →
Assignment of Assignor's Interest Sep 1, 2005
From: BRAUN, GUNNAR; GREIVE, VOLKER; HOFFMANN, ANDREAS
To: COWARE, INC.
Reel/Frame 016942/0497 →
Assignment of Assignor's Interest Sep 23, 2005
From: BRAUN, GUNNAR; NOHL, ACHIM; CENG, JIANGJIANG; HOFFMANN, ANDREAS
To: COWARE, INC.
Reel/Frame 017540/0711 →
Re-Record to Correct Inventor Name Previously Recorded at Reel/Frame 016415/0440 Nov 1, 2005
From: GREIVE, VOLKER; NOHL, ACHIM
To: COWARE, INC.
Reel/Frame 016904/0418 →
Assignment of Assignor's Interest Dec 9, 2005
From: BRAUN, GUNNAR; HOFFMANN, ANDREAS; GREIVE, VOLKER; LEUPERS, RAINER
To: COWARE, INC.
Reel/Frame 017327/0021 →
Assignment of Assignor's Interest Feb 17, 2006
From: KUMAR, RAJESH; JAIN, SANJAY KUMAR
To: COWARE, INC.
Reel/Frame 017601/0042 →
Assignment of Assignor's Interest Jul 13, 2006
From: BRAUN, GUNNAR; FIEDLER, FRANK; HOFFMANN, ANDREAS; INTRATER, GIDEON
To: MIPS TECHNOLOGIES, INC.; COWARE, INC.
Reel/Frame 018091/0548 →
Corrective Assignment to Correct Name of Inventor Karl Aug 4, 2006
From: VERMEERSCH, DIRK; VAN ROMPAY, KARL
To: COWARE, INC.
Reel/Frame 018147/0200 →
Assignment of Assignor's Interest Sep 11, 2006
From: BRAUN, GUNNAR; FIEDLER, FRANK; HOFFMANN, ANDREAS; INTRATER, GIDEON
To: MIPS TECHNOLOGIES, INC.; COWARE, INC.
Reel/Frame 018280/0806 →
Assignment of Assignor's Interest May 29, 2007
From: LIPPETT, MARK DAVID
To: COWARE, INC.
Reel/Frame 019381/0440 →
Assignment of Assignor's Interest Jun 14, 2007
From: COWARE, INC.
To: FUJITSU LIMITED
Reel/Frame 019460/0086 →