Run-time switching for simulation with dynamic run-time accuracy adjustment
View Patent ↗Systems and methods for run-time switching for simulation with dynamic run-time accuracy adjustment. In one embodiment, a computer implemented method performs a simulation of a computer instruction executing on a simulated hardware design by a first simulation model, wherein the first simulation model provides first timing information of the simulation. The first timing information is stored to a computer usable media. A pending subsequent simulation of the instruction is detected. Responsive to the presence of the first timing information in the computer usable media, the computer instruction is simulated by a second simulation model, wherein the second simulation model provides less accurate second timing information of the simulation than the first simulation model. The simulation run time information is updated for the subsequent simulation with the first timing information.
1. A computer implemented method comprising:
performing a simulation of a computer instruction executing on a simulated hardware design by a first simulation model, wherein said first simulation model provides first timing information of said simulation;
storing said first timing information to a computer usable medium;
detecting a pending subsequent simulation of said instruction;
responsive to the presence of said first timing information in said computer usable medium, simulating said computer instruction by a second simulation model, wherein said second simulation model provides less accurate second timing information of said simulation than said first simulation model; and
updating simulation run time information for said subsequent simulation with said first timing information.
2. The method of claim 1 wherein said second simulation model provides no said second timing information.
3. The method of claim 2 wherein said second simulation model is an instruction accurate model.
4. The method of claim 1 wherein said first simulation model is a cycle accurate model.
5. The method of claim 1 wherein at least one of said first and second simulation models is a commercially available simulation model.
6. The method of claim 5 wherein said at least one of said first and second simulation models is provided by a supplier of said hardware design.
7. An article of manufacture including a computer readable medium having instructions stored therein that, if executed on a computing device cause the computing device to perform operations comprising:
performing a simulation of a computer instruction executing on a simulated hardware design by a first simulation model, wherein said first simulation model provides first timing information of said simulation;
storing said first timing information to a computer usable medium;
detecting a pending subsequent simulation of said instruction;
responsive to the presence of said first timing information in said computer usable medium, simulating said computer instruction by a second simulation model, wherein said second simulation model provides less accurate second timing information of said simulation than said first simulation model; and
updating simulation run time information for said subsequent simulation with said first timing information.
8. The article of manufacture of claim 7 wherein said second simulation model provides no said second timing information.
9. The article of manufacture of claim 8 wherein said second simulation model is an instruction accurate model.
10. The article of manufacture of claim 7 wherein said first simulation model is a cycle accurate model.
11. The article of manufacture of claim 10 wherein at least one of said first and second simulation models is a commercially available simulation model.
12. The article of manufacture of claim 7 wherein said at least one of said first and second simulation models is provided by a supplier of said hardware design.
13. A computer implemented simulation method comprising:
switching from a processor simulation by a first simulation model that provides first timing information for instructions to a processor simulation by a second simulation model which provides less accurate second timing information than said first simulation model, said switching being responsive to an existence in a computer memory, of said first timing information for a next instruction to be simulated.
14. The method of claim 13 wherein said timing information was created by a previous simulation of said next instruction by the first simulation model.
15. The method of claim 14 wherein said first simulation model comprises a cycle accurate simulation.
16. The method of claim 14 wherein said second simulation model does not provide instruction timing information.
17. The method of claim 14 wherein said second simulation model comprises an instruction accurate simulation.
18. The method of claim 14 further comprising storing said timing information for later access.
19. The method of claim 13 further comprising:
switching from said processor simulation by said second simulation model to said processor simulation by said first simulation model responsive to absence of timing information for the next instruction to be simulated.
20. The method of claim 19 wherein said switching from said processor simulation by said second simulation model to said processor simulation by said first simulation model and said switching from said processor simulation by said first simulation model to said processor simulation by said second simulation model are done responsive to a user mode setting command.