Charge pump with fibonacci number multiplication
View Patent ↗A charge pump includes a plurality of capacitors that are alternately charged and serially coupled. When serially coupled, the voltage across a given capacitor will equal the voltage at its negative terminal and the voltage across the preceding capacitor.
1. A method of generating voltages, comprising in order:
(a) charging a first plurality of capacitors,
(b) serially coupling a first plurality of charged capacitors such that, within the first plurality of charged capacitors, a positive terminal of a charged first capacitor couples to a negative tenninal of a charged second capacitor and so on,
(c) charging a second plurality of capacitors from voltages produced by the first plurality of serially-coupled charged capacitors,
(d) serially coupling the second plurality of charged capacitors such that, within the second plurality of capacitors, a positive terminal of a charged first capacitor couples to a negative terminal of a charged second capacitor and so on,
(e) charging the first plurality of capacitors from voltages produced by the second plurality of serially-coupled charged capacitors, and
(f) repeating (b)–(e) in order a multiple number of times.
2. The method of claim 1 , wherein (b) and (c) occur during a first phase of a clock signal and (d) and (e) occur during a second phase of the clock signal.
3. The method of claim 1 , wherein, for an integer k greater than one, the voltage across the kth capacitor in the first plurality of capacitors during (b) equals the voltage at its negative terminal plus the voltage across the (k−1)th capacitor in the first plurality of capacitors.
4. The method of claim 3 , wherein, for an integer m greater than 1, the voltage across the mth capacitor in the second plurality of capacitors during (d) equals the voltage at its negative terminal plus the voltage across the (m−1)th capacitor in the second plurality of capacitors.
5. The method of claim 4 , wherein (b) and (c) occur during a first phase of a clock signal and (d) and (e) occur during a second phase of the clock signal.