IP Library › Assignment 038813/0004
Patent Assignment
Reel/Frame 038813/0004

CHANGE OF NAME

Recorded: 2016-05-25 Received: 2016-05-25 Pages: 17
Assignor
SANDISK TECHNOLOGIES INC
Executed: 2016-05-16
Assignee
SANDISK TECHNOLOGIES LLC
6900 DALLAS PARKWAY, SUITE 325, PLANO, TX, 75024, UNITED STATES
Covered Applications (100)
Auto-Adaptive Virtual Desktop Persistence
App. No. 15/173,826
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READ AND ERASE VERIFY METHODS AND CIRCUITS SUITABLE FOR LOW VOLTAGE NON-VOLATILE MEMORIES
App. No. 10/552,948
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DIE PACKAGE WITH ASYMMETRIC LEADFRAME CONNECTION
App. No. 11/170,897
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SUBSTRATE WARPAGE CONTROL AND CONTINUOUS ELECTRICAL ENHANCEMENT
App. No. 11/171,819
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METHOD AND SYSTEM FOR MANAGING PARTITIONS IN A STORAGE DEVICE
App. No. 11/170,221
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METHOD OF DEPOSITING GERMANIUM FILMS
App. No. 11/159,031
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METHOD AND APPARATUS FOR PROGRAMMING A MEMORY ARRAY
App. No. 11/158,396
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AREA EFFICIENT CHARGE PUMP
App. No. 11/158,557
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VOLATILE MEMORY CELL TWO-PASS WRITING METHOD
App. No. 11/157,317
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COMPENSATION CURRENTS IN NON-VOLATILE MEMORY READ OPERATIONS
App. No. 11/157,033
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FLOATING BODY MEMORY CELL SYSTEM AND METHOD OF MANUFACTURE
App. No. 11/157,293
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SEGMENTED METAL BITLINES
App. No. 11/152,278
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DECODING CIRCUIT FOR NON-BINARY GROUPS OF MEMORY LINE DRIVERS
App. No. 11/146,952
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METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS
App. No. 11/148,001
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POST-DEPOSITION ENCAPSULATION OF NANOSTRUCTURES: COMPOSITIONS, DEVICES AND SYSTEMS INCORPORATING SAME
App. No. 11/147,670
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STARTING PROGRAM VOLTAGE SHIFT WITH CYCLING OF NON-VOLATILE MEMORY
App. No. 11/144,264
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TFT CHARGE STORAGE MEMORY CELL HAVING HIGH-MOBILITY CORRUGATED CHANNEL
App. No. 11/143,355
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SYSTEM AND METHOD FOR RECEIVING DIGITAL CONTENT
App. No. 11/137,916
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SYSTEM-IN-A-PACKAGE BASED FLASH MEMORY CARD
App. No. 11/133,576
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FLASH MEMORY ARRAY WITH INCREASED COUPLING BETWEEN FLOATING AND CONTROL GATES
App. No. 11/132,522
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METHOD OF ASSEMBLING SEMICONDUCTOR DEVICES WITH LEDS
App. No. 11/129,637
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SELECTIVE APPLICATION OF PROGRAM INHIBIT SCHEMES IN NON-VOLATILE MEMORY
App. No. 11/127,743
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NOVEL METHOD AND STRUCTURE FOR EFFICIENT DATA VERIFICATION OPERATION FOR NON-VOLATILE MEMORIES
App. No. 11/125,644
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DETECTING OVER PROGRAMMED MEMORY
App. No. 11/124,709
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NON-VOLATILE MEMORY WITH IMPROVED PROGRAMMING AND METHOD THEREFOR
App. No. 11/126,044
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SCALABLE SELF-ALIGNED DUAL FLOATING GATE MEMORY CELL ARRAY AND METHODS OF FORMING THE ARRAY
App. No. 11/111,129
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APPARATUS AND METHODS FOR ADAPTIVE TRIP POINT DETECTION
App. No. 11/106,288
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RIGID WAVE PATTERN DESIGN ON CHIP CARRIER SUBSTRATE AND PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR AND ELECTRONIC SUB-SYSTEM PACKAGING
App. No. 11/106,699
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NOVEL MULTI-STATE MEMORY
App. No. 11/105,855
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WORD LINE ARRANGEMENT HAVING MULTI-LAYER WORD LINE SEGMENTS FOR THREE-DIMENSIONAL MEMORY ARRAY
App. No. 11/103,185
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WORD LINE ARRANGEMENT HAVING SEGMENTED WORD LINES
App. No. 11/103,184
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WORD LINE ARRANGEMENT HAVING MULTI-LAYER WORD LINE SEGMENTS FOR THREE-DIMENSIONAL MEMORY ARRAY
App. No. 11/103,249
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FASTER PROGRAMMING OF HIGHER LEVEL STATES IN MULTI-LEVEL CELL FLASH MEMORY
App. No. 11/099,259
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COMPENSATING FOR COUPLING IN NON-VOLATILE STORAGE
App. No. 11/099,239
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COMPENSATING FOR COUPLING DURING READ OPERATIONS OF NON-VOLATILE MEMORY
App. No. 11/099,133
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READ OPERATION FOR NON-VOLATILE STORAGE THAT INCLUDES COMPENSATION FOR COUPLING
App. No. 11/099,049
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NON-VOLATILE MEMORY AND METHOD WITH CONTROL GATE COMPENSATION FOR SOURCE LINE BIAS ERRORS
App. No. 11/097,502
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USE OF DATA LATCHES IN MULTI-PHASE PROGRAMMING OF NON-VOLATILE MEMORIES
App. No. 11/097,517
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USE OF DATA LATCHES IN CACHE OPERATIONS OF NON-VOLATILE MEMORIES
App. No. 11/097,590
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NON-VOLATILE MEMORY AND METHOD WITH COMPENSATION FOR SOURCE LINE BIAS ERRORS
App. No. 11/097,038
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TRANSISTOR LAYOUT CONFIGURATION FOR TIGHT-PITCHED MEMORY ARRAY LINES
App. No. 11/095,905
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METHOD AND APPARATUS FOR INCORPORATING BLOCK REDUNDANCY IN A MEMORY ARRAY
App. No. 11/095,907
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MASKING OF REPEATED OVERLAY AND ALIGNMENT MARKS TO ALLOW REUSE OF PHOTOMASKS IN A VERTICAL STRUCTURE
App. No. 11/097,496
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INTEGRATED CIRCUIT MEMORY ARRAY CONFIGURATION INCLUDING DECODING COMPATIBILITY WITH PARTIAL IMPLEMENTATION OF MULTIPLE MEMORY LAYERS
App. No. 11/095,415
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METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE
App. No. 11/090,526
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METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES
App. No. 11/089,771
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MOUNTING FOR DUAL HARD DRIVES
App. No. 11/086,017
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DEEP WORDLINE TRENCH TO SHIELD CROSS COUPLING BETWEEN ADJACENT CELLS FOR SCALED NAND
App. No. 11/086,648
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NON-VOLATILE MEMORY AND METHOD WITH POWER-SAVING READ AND PROGRAM-VERIFY OPERATIONS
App. No. 11/083,514
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PROGRAMMING NON-VOLATILE MEMORY
App. No. 11/081,134
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BOTTOM-GATE SONOS-TYPE CELL HAVING A SILICIDE GATE
App. No. 11/077,901
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PARTITION OF NON-VOLATILE MEMORY ARRAY TO REDUCE BIT LINE CAPACITANCE
App. No. 11/078,173
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PORTABLE MEMORY STORAGE DEVICE WITH BIOMETRIC IDENTIFICATION SECURITY
App. No. 11/076,221
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UNIVERSAL NON-VOLATILE MEMORY CARD USED WITH VARIOUS DIFFERENT STANDARD CARDS CONTAINING A MEMORY CONTROLLER
App. No. 11/075,438
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MULTI-STATE NON-VOLATILE INTEGRATED CIRCUIT MEMORY SYSTEMS THAT EMPLOY DIELECTRIC STORAGE ELEMENTS
App. No. 11/075,423
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MULTI-STATE NON-VOLATILE INTEGRATED CIRCUIT MEMORY SYSTEMS THAT EMPLOY DIELECTRIC STORAGE ELEMENTS
App. No. 11/075,427
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CHARGE PUMP WITH FIBONACCI NUMBER MULTIPLICATION
App. No. 11/069,660
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APPARATUS, SYSTEM AND METHOD FOR SECURING DIGITAL DOCUMENTS IN A DIGITAL APPLIANCE
App. No. 11/067,298
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WRITABLE TRACKING CELLS
App. No. 11/064,529
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METHOD FOR PATTERNING SUBMICRON PILLARS
App. No. 11/061,952
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DIRECT DATA FILE STORAGE IN FLASH MEMORIES
App. No. 11/060,249
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PIPELINED PARALLEL PROGRAMMING OPERATION IN A NON-VOLATILE MEMORY SYSTEM
App. No. 11/058,359
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TECHNIQUES FOR REDUCING EFFECTS OF COUPLING BETWEEN STORAGE ELEMENTS OF ADJACENT ROWS OF MEMORY CELLS
App. No. 11/055,776
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METHOD OF REDUCING DISTURBS IN NON-VOLATILE MEMORY
App. No. 11/054,084
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SECURE MEMORY CARD WITH LIFE CYCLE PHASES
App. No. 11/053,273
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SOURCE SIDE SELF BOOSTING TECHNIQUE FOR NON-VOLATILE MEMORY
App. No. 11/049,802
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DATA-AWARE CACHE STATE MACHINE
App. No. 11/047,433
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METHOD AND APPARATUS FOR ADJUSTING TIMING SIGNAL BETWEEN MEDIA CONTROLLER AND STORAGE MEDIA
App. No. 11/043,709
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MULTIPLE MODE COMMUNICATION SYSTEM
App. No. 11/044,152
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VOLTAGE REGULATOR WITH BYPASS MODE
App. No. 11/042,610
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STRUCTURE AND METHOD FOR BIASING PHASE CHANGE MEMORY ARRAY FOR RELIABLE WRITING
App. No. 11/040,262
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FORMING NONVOLATILE PHASE CHANGE MEMORY CELL HAVING A REDUCED THERMAL CONTACT AREA
App. No. 11/040,465
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WRITE-ONCE NONVOLATILE PHASE CHANGE MEMORY ARRAY
App. No. 11/040,256
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DELIVERY OF A MESSAGE TO A USER OF A PORTABLE DATA STORAGE DEVICE AS A CONDITION OF ITS USE
App. No. 11/035,701
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TECHNIQUES OF RECOVERING DATA FROM MEMORY CELLS AFFECTED BY FIELD COUPLING WITH ADJACENT MEMORY CELLS
App. No. 11/028,906
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DUAL-MODE DECODER CIRCUIT, INTEGRATED CIRCUIT MEMORY ARRAY INCORPORATING SAME, AND RELATED METHODS OF OPERATION
App. No. 11/026,493
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INTEGRATED CIRCUIT INCLUDING MEMORY ARRAY INCORPORATING MULTIPLE TYPES OF NAND STRING STRUCTURES
App. No. 11/026,492
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ON-CHIP DATA GROUPING AND ALIGNMENT
App. No. 11/026,549
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APPARATUS AND METHOD FOR HIERARCHICAL DECODING OF DENSE MEMORY ARRAYS USING MULTIPLE LEVELS OF MULTIPLE-HEADED DECODERS
App. No. 11/026,470
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WORD LINE COMPENSATION IN NON-VOLATILE MEMORY ERASE OPERATIONS
App. No. 11/025,620
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REDUCING FLOATING GATE TO FLOATING GATE COUPLING EFFECT
App. No. 11/021,872
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SUBSTRATE ELECTRON INJECTION TECHNIQUES FOR PROGRAMMING NON-VOLATILE CHARGE STORAGE MEMORY CELLS
App. No. 11/021,193
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Fat analysis for optimized sequential cluster management
App. No. 11/022,369
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MULTI-THICKNESS DIELECTRIC FOR SEMICONDUCTOR MEMORY
App. No. 11/020,402
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LOW-VOLTAGE, MULTIPLE THIN-GATE OXIDE AND LOW-RESISTANCE GATE ELECTRODE
App. No. 11/021,693
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ERASED SECTOR DETECTION MECHANISMS
App. No. 11/020,345
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SEMICONDUCTOR PACKAGE USING TERMINALS FORMED ON A CONDUCTIVE LAYER OF A CIRCUIT BOARD
App. No. 11/021,169
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METHOD FOR COPYING DATA IN REPROGRAMMABLE NON-VOLATILE MEMORY
App. No. 11/022,350
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NANO-ENABLED MEMORY DEVICES AND ANISOTROPIC CHARGE CARRYING ARRAYS
App. No. 11/018,572
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SYSTEM AND METHOD FOR USE OF ON-CHIP NON-VOLATILE MEMORY WRITE CACHE
App. No. 11/021,200
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OFF-CHIP DATA RELOCATION
App. No. 11/022,462
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CURRENT-LIMITED LATCH
App. No. 11/019,990
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APPARATUS AND METHOD FOR MEMORY OPERATIONS USING ADDRESS-DEPENDENT CONDITIONS
App. No. 11/015,440
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NONVOLATILE MEMORY CELL COMPRISING A REDUCED HEIGHT VERTICAL DIODE
App. No. 11/015,824
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SCRATCH PAD BLOCK
App. No. 11/016,285
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MEMORY SENSING CIRCUIT AND METHOD FOR LOW VOLTAGE OPERATION
App. No. 11/015,199
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DATA RUN PROGRAMMING
App. No. 11/016,271
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CLUSTER AUTO-ALIGNMENT FOR STORING ADDRESSABLE DATA PACKETS IN A NON-VOLATILE MEMORY ARRAY
App. No. 11/015,211
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PIPELINED PROGRAMMING OF NON-VOLATILE MEMORIES USING EARLY DATA
App. No. 11/013,125
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MEMORY DEVICE WITH SECTOR POINTER STRUCTURE
App. No. 11/009,439
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