Voltage regulator with bypass mode

1. A step down voltage regulator comprising devices designed to operate at a maximum device voltage lower than a supply voltage, comprising:

an output regulation device coupled to the supply voltage and an output;

an output device protection circuit responsive to the supply voltage and the output to ensure that the maximum device voltage of the output regulation device is not exceeded; and

a bypass circuit having a bypass output device and being coupled to the supply voltage, the bypass circuit including protection circuitry to ensure that the maximum device voltage of the bypass output device is not exceeded, the bypass circuit enabled when the supply voltage is at said maximum device voltage and disabled above the maximum device voltage.

2. The regulator of claim 1 wherein the output regulation device comprises a p-channel transistor.

3. The regulator of claim 2 wherein the p-channel transistor has an operating maximum rated voltage in a range of 2.7-3.6 volts and the supply voltage is in a range of 4.4-5.25 volts.

4. The regulator of claim 2 wherein the output device protection circuit includes a gate-source protection component.

5. The regulator of claim 2 wherein the output device protection circuit includes a gate-drain protection component.

6. The regulator of claim 2 wherein the bypass output device is a p-channel transistor having a lower output resistance than said output regulation device.

7. The regulator of claim 6 wherein the bypass output device is several times greater in size than the output regulation device.

8. The regulator of claim 1 further including a voltage detector outputting a signal indicating whether the supply voltage is at said maximum device voltage or a greater voltage.

9. The regulator of claim 8 wherein said output device protection circuit and said bypass circuit are coupled to said signal.

10. The regulator of claim 9 wherein said bypass circuit is enabled or disabled based on said signal.

11. The regulator of claim 9 wherein said output protection circuit and said protection circuitry are enabled by said signal.

12. A voltage regulator supplying an output voltage lower than a supply voltage, comprising:

a first output device and a second output device, each designed to operate at a maximum rated voltage lower than the supply voltage;

protection circuitry coupled to the first output device and the second output device regulating, the protection circuitry regulating a gate voltage of the first output device and a second gate voltage of the second output device relative to a drain load and a source voltage on the first output device and a drain load and a source voltage on the second output device so as to not exceed the maximum rated voltage;

a voltage detector coupled to the supply voltage and at least the second output device, enabling the second output device when the supply voltage is at a voltage less than a maximum operating voltage for the first and second output devices.

13. The regulator of claim 12 wherein the output devices comprise p-channel transistors.

14. The regulator of claim 13 wherein the p-channel transistors have an operating maximum rated voltage in a range of 2.7-3.6 volts and the supply voltage is in a range of 4.4-5.25 volts.

15. The regulator of claim 12 wherein the second output device is a p-channel transistor having a lower output resistance than said first output device.

16. The regulator of claim 15 wherein the second output device is approximately three times greater in size than the first output device.

17. The regulator of claim 12 wherein the voltage detector outputs a signal indicating whether the supply voltage said maximum operating voltage or a greater voltage.

18. The regulator of claim 12 wherein said protection circuitry is coupled to said signal.

19. A memory system including a control path and a data path to a host device, and receiving a supply voltage from the host device, comprising:

a voltage regulator including

a voltage input coupled to the supply voltage;

an output device having a maximum device operating voltage less than a maximum possible supply voltage and coupled to a regulator output; p 2 a bypass device having the maximum device operating voltage and coupled to the regulator output;

a protection circuit coupled to the voltage input, the bypass device and the output device, the protection circuit comprising a plurality of output control devices operating at maximum rated voltages less than the voltage provided by the host at the input; and

a voltage detector coupled to the supply voltage outputting a signal indicating whether a level of the supply voltage exceeds the maximum device voltage; and

wherein said bypass circuit is enabled or disabled based on said signal.

20. The memory system of claim 19 wherein the output device and the bypass device comprise a p-channel transistors.

21. The memory system of claim 20 wherein the p-channel transistors have an operating maximum rated voltage in a range of 2.7-3.6 volts and the supply voltage is in a range of 4.4-5.25 volts.

22. The regulator of claim 19 wherein the bypass device is a p-channel transistor having a lower output resistance than said output regulation device.

23. The regulator of claim 22 wherein the bypass output device is several times greater in size than the output regulation device.

24. A peripheral device for a host system including a voltage regulator circuit, comprising:

a functional component;

a voltage regulator having an output regulation device and a bypass device coupled to the supply voltage and an output supply voltage input and an output;

an output device protection circuit responsive to the supply voltage and the output to ensure that the maximum rated voltage of the output regulation device is not exceeded; and

a bypass circuit having including protection circuitry enabled when the supply is at said maximum rated voltage;

wherein the functional component is a memory system.

25. The peripheral device of claim 24 wherein the memory system includes a controller and a memory array.

26. The peripheral device of claim 24 wherein the memory system is a pc card.

27. The peripheral device of claim 24 wherein the memory system is compact flash card.

28. The peripheral device of claim 24 wherein the memory system is a secure digital card.

29. The peripheral device of claim 24 wherein the memory system is a smart media card.

30. The peripheral device of claim 24 wherein the memory system is a memory stick.

31. The peripheral device of claim 24 wherein the memory system is a USB flash drive.

32. A memory system, comprising:

a controller;

a memory array; and

a voltage regulator including a plurality of devices operating at maximum rated voltages less than a supply voltage and having an output regulation device coupled to the supply voltage and an output;

an output device protection circuit responsive to the supply voltage and the output to ensure that the maximum rated voltage of the output regulation device is not exceeded; and

a bypass circuit having a bypass output device and being coupled to the supply voltage, the bypass circuit including protection circuitry to ensure that the maximum device voltage of the bypass output device is not exceeded, the bypass circuit enabled when the supply voltage is at said maximum rated voltage and disabled above said maximum device voltage.

33. A peripheral device, comprising:

a universal serial bus interface;

a memory array having an input operating voltage; and

a voltage regulator including an output regulation device coupled to the supply voltage and the memory array, the voltage regulator including

an output device protection circuit responsive to the supply voltage to ensure that a maximum operating voltage of the output regulation device is not exceeded; and

a bypass circuit having a bypass output device coupled to the memory array, the circuit being coupled to the supply voltage, the bypass circuit including protection circuitry to ensure that the maximum device voltage of the bypass output device is not exceeded, the bypass circuit enabled when the supply is at said maximum voltage and disabled above said maximum device voltage.