Decoding circuit for non-binary groups of memory line drivers

1. An integrated circuit comprising:

a memory array comprising a plurality of array lines;

a number of array line driver circuits coupled with the plurality of array lines, wherein the number is other than an integral power of two; and

control circuitry configured to select one of the array line driver circuits, wherein the control circuitry comprises a binary decoder comprising a plurality of outputs, wherein each output drives a non-binary number of array line driver circuits.

2. The integrated circuit of claim 1 , wherein the number comprises six.

3. The integrated circuit of claim 1 , wherein the control circuitry is operative to leave holes in a decode map.

4. The integrated circuit of claim 1 , wherein the control circuitry further comprises a pre-binary-decoder portion operative to perform a non-binary arithmetic operation.

5. The integrated circuit of claim 1 , wherein the plurality of array lines comprise word lines, and wherein the plurality of array line driver circuits comprise word line driver circuits.

6. The integrated circuit of claim 1 further comprising:

circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder.

7. The integrated circuit of claim 1 , wherein the memory array comprises a three-dimensional memory array comprising a monolithic semiconductor integrated circuit incorporating more than one memory plane formed above and below each other and above a semiconductor substrate, and wherein the plurality of array line driver circuits and the decoder circuit are disposed within the semiconductor substrate under the three-dimensional memory array.

8. The integrated circuit of claim 1 , wherein the memory array comprises a continuous matrix of memory cells.

9. The integrated circuit of claim 4 , wherein the non-binary arithmetic operation comprises a modulo three remainder operation.

10. The integrated circuit of claim 6 , wherein the non-binary arithmetic operation comprises a divide-by-three operation.

11. An integrated circuit comprising:

a memory array comprising a plurality of array lines;

a non-binary number of array line driver circuits coupled with the plurality of array lines; and

a decoder circuit coupled with the non-binary number of array line driver circuits, the decoder circuit comprising:

a binary decoder; and

circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder.

12. The integrated circuit of claim 11 , wherein the number comprises six.

13. The integrated circuit of claim 11 , wherein the non-binary arithmetic operation comprises a modulo three remainder operation.

14. The integrated circuit of claim 11 , wherein the plurality of array lines comprise word lines, and wherein the plurality of array line driver circuits comprise word line driver circuits.

15. The integrated circuit of claim 11 further comprising:

a second binary decoder, the second binary decoder operative to select a group of array lines; and

second circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation of the second circuitry is provided as input to the binary decoder.

16. The integrated circuit of claim 11 , wherein the memory array comprises a three-dimensional memory array comprising a monolithic semiconductor integrated circuit incorporating more than one memory plane formed above and below each other and above a semiconductor substrate, wherein the plurality of array line driver circuits and the decoder circuit are disposed within the semiconductor substrate under the three-dimensional memory array.

17. The integrated circuit of claim 11 , wherein the memory array comprises a continuous matrix of memory cells.

18. The integrated circuit of claim 15 , wherein the non-binary arithmetic operation performed by the second binary decoder comprises a divide-by-three operation.

19. An integrated circuit comprising:

a binary decoder; and

circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder.

20. The integrated circuit of claim 19 , wherein the binary decoder comprises a post-decode portion comprising a non-binary multiplicity.

21. The integrated circuit of claim 19 , wherein the binary decoder is operative to select one of a non-binary number of array line driver circuits coupled with plurality of array lines of a memory array.

22. The integrated circuit of claim 19 , wherein the non-binary arithmetic operation comprises a modulo three remainder operation.

23. The integrated circuit of claim 19 further comprising a memory array comprising a continuous matrix of memory cells.

24. An integrated circuit comprising:

a memory array comprising a plurality of array lines;

a plurality of groups of array line driver circuits coupled with the plurality of array lines;

a number of array line driver circuits in at least one of the plurality of groups of array line driver circuits, wherein the number is other than an integral power of two; and

control circuitry configured to select one of the array line driver circuits, wherein the control circuitry comprises a binary decoder comprising a plurality of outputs, wherein each output drives a non-binary number of array line driver circuits.

25. The integrated circuit of claim 24 , wherein the array line driver circuits in at least one of the plurality of groups share a control input signal provided by the control circuitry.

26. The integrated circuit of claim 24 , wherein the memory array comprises a plurality of sub arrays, and wherein at least one of the plurality of the groups of array line driver circuits support one or two sub arrays of memory cells.

27. The integrated circuit of claim 24 , wherein the memory array comprises a continuous matrix of memory cells.