Patent Assignment
Reel/Frame 018950/0686
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECTIVE MERGER TO ADD PAGES TO THE MERGER DOCUMENT PREVIOUSLY RECORDED PREVIOUSLY RECORDED ON REEL 017544 FRAME 0769. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER.
Recorded: 2007-03-02
Received: 2007-03-02
Pages: 52
Assignor
MATRIX SEMICONDUCTOR, INC.
Executed: 2005-10-20
Assignee
SANDISK 3D LLC
140 CASPIAN COURT, SUNNYVALE, CA, 94089, UNITED STATES
Covered Applications
(100)
VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION
App. No. 11/354,470
→
VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION
App. No. 11/355,214
→
METHOD FOR PATTERNING SUBMICRON PILLARS
PCTPCTUS2006004195
→
STRUCTURE AND METHOD FOR BIASING PHASE CHANGE MEMORY ARRAY FOR RELIABLE WRITING
PCTPCTUS2006000776
→
A NON-VOLATILE MEMORY CELL COMPRISING A DIELECTRIC LAYER AND A PHASE CHANGE MATERIAL IN SERIES
PCTPCTUS2006000774
→
LASER ANNEAL OF VERTICALLY ORIENTED SEMICONDUCTOR STRUCTURES WHILE MAINTAINING A DOPANT PROFILE
App. No. 11/303,229
→
APPARATUS AND METHOD FOR HIERARCHICAL DECODING OF DENSE MEMORY ARRAYS USING MULTIPLE LEVELS OF MULTIPLE-HEADED DECODERS
PCTPCTUS2005045564
→
METHOD TO FORM TOPOGRAPHY IN A DEPOSITED LAYER ABOVE A SUBSTRATE
App. No. 11/298,015
→
DEPOSITED SEMICONDUCTOR STRUCTURE TO MINIMIZE N-TYPE DOPANT DIFFUSION AND METHOD OF MAKING
App. No. 11/298,331
→
APPARATUS AND METHOD FOR MEMORY OPERATIONS USING ADDRESS-DEPENDENT CONDITIONS
PCTPCTUS2005043074
→
DEVICES HAVING REVERSIBLE RESISTIVITY-SWITCHING METAL OXIDE OR NITRIDE LAYER WITH ADDED METAL
App. No. 11/287,452
→
Vertical diode doped with antimony to avoid or limit dopant diffusion
App. No. 11/271,078
→
Low-density, high-resistivity titanium nitride layer for use as a contact for low-leakage dielectric layers and method of making
App. No. 11/249,212
→
FUSE MEMORY CELL COMPRISING A DIODE, THE DIODE SERVING AS THE FUSE ELEMENT
PCTPCTUS2005034936
→
METHOD TO MINIMIZE FORMATION OF RECESS AT SURFACE PLANARIZED BY CHEMICAL MECHANICAL PLANARIZATION
App. No. 11/237,169
→
MEMORY CELL COMPRISING SWITCHABLE SEMICONDUCTOR MEMORY ELEMENT WITH TRIMMABLE RESISTANCE
App. No. 11/237,167
→
SELECTIVE OXIDATION OF SILICON IN DIODE, TFT, AND MONOLITHIC THREE DIMENSIONAL MEMORY ARRAYS
App. No. 11/237,162
→
ULTRATHIN CHEMICALLY GROWN OXIDE FILM AS A DOPANT DIFFUSION BARRIER IN SEMICONDUCTOR DEVICES
App. No. 11/215,951
→
METHOD AND APPARATUS FOR USING A ONE-TIME OF FEW-TIME PROGRAMMABLE MEMORY WITH A HOST DEVICE DESIGNED FOR ERASABLE/REWRITABLE MEMORY
PCTPCTUS2005026054
→
Memory cell comprising a thin film three-terminal switching device having a metal source and /or drain region
App. No. 11/179,095
→
THREE-DIMENSIONAL NON-VOLATILE SRAM INCORPORATING THIN-FILM DEVICE LAYER
App. No. 11/179,360
→
SWITCHABLE RESISTIVE MEMORY WITH OPPOSITE POLARITY WRITE PULSES
App. No. 11/179,122
→
APPARATUS AND METHOD FOR READING AN ARRAY OF NONVOLATILE MEMORY CELLS INCLUDING SWITCHABLE RESISTOR MEMORY ELEMENTS
App. No. 11/179,123
→
Method of plasma etching transition metals and their compounds
App. No. 11/179,423
→
APPARATUS AND METHOD FOR PROGRAMMING AN ARRAY OF NONVOLATILE MEMORY CELLS INCLUDING SWITCHABLE RESISTOR MEMORY ELEMENTS
App. No. 11/179,077
→
INTEGRATED CIRCUIT EMBODYING A NON-VOLATILE MEMORY CELL
App. No. 11/175,688
→
Memory with high dielectric constant antifuses and method for using at low voltage
App. No. 11/173,973
→
REVERSE-BIAS METHOD FOR WRITING MEMORY CELLS IN A MEMORY ARRAY
App. No. 11/174,234
→
MEMORY CELL WITH HIGH-K ANTIFUSE FOR REVERSE BIAS PROGRAMMING
App. No. 11/174,240
→
METHOD OF DEPOSITING GERMANIUM FILMS
App. No. 11/159,031
→
METHOD AND APPARATUS FOR PROGRAMMING A MEMORY ARRAY
App. No. 11/158,396
→
VOLATILE MEMORY CELL TWO-PASS WRITING METHOD
App. No. 11/157,317
→
FLOATING BODY MEMORY CELL SYSTEM AND METHOD OF MANUFACTURE
App. No. 11/157,293
→
Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material
App. No. 11/148,530
→
DECODING CIRCUIT FOR NON-BINARY GROUPS OF MEMORY LINE DRIVERS
App. No. 11/146,952
→
Rewriteable memory cell comprising a transistor and resistance-switching material in series
App. No. 11/143,269
→
TFT CHARGE STORAGE MEMORY CELL HAVING HIGH-MOBILITY CORRUGATED CHANNEL
App. No. 11/143,355
→
Rewriteable memory cell comprising a diode and a resistance-switching material
App. No. 11/125,939
→
High-density nonvolatile memory array fabricated at low temperature comprising semiconductor diodes
App. No. 11/125,606
→
Methods and apparatus for dynamically reconfiguring a charge pump during output transients
App. No. 11/125,000
→
APPARATUS AND METHODS FOR ADAPTIVE TRIP POINT DETECTION
App. No. 11/106,288
→
WORD LINE ARRANGEMENT HAVING MULTI-LAYER WORD LINE SEGMENTS FOR THREE-DIMENSIONAL MEMORY ARRAY
App. No. 11/103,185
→
WORD LINE ARRANGEMENT HAVING SEGMENTED WORD LINES
App. No. 11/103,184
→
WORD LINE ARRANGEMENT HAVING MULTI-LAYER WORD LINE SEGMENTS FOR THREE-DIMENSIONAL MEMORY ARRAY
App. No. 11/103,249
→
TRANSISTOR LAYOUT CONFIGURATION FOR TIGHT-PITCHED MEMORY ARRAY LINES
App. No. 11/095,905
→
METHOD AND APPARATUS FOR INCORPORATING BLOCK REDUNDANCY IN A MEMORY ARRAY
App. No. 11/095,907
→
MASKING OF REPEATED OVERLAY AND ALIGNMENT MARKS TO ALLOW REUSE OF PHOTOMASKS IN A VERTICAL STRUCTURE
App. No. 11/097,496
→
INTEGRATED CIRCUIT MEMORY ARRAY CONFIGURATION INCLUDING DECODING COMPATIBILITY WITH PARTIAL IMPLEMENTATION OF MULTIPLE MEMORY LAYERS
App. No. 11/095,415
→
METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE
App. No. 11/090,526
→
METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES
App. No. 11/089,771
→
BOTTOM-GATE SONOS-TYPE CELL HAVING A SILICIDE GATE
App. No. 11/077,901
→
METHOD FOR PATTERNING SUBMICRON PILLARS
App. No. 11/061,952
→
STRUCTURE AND METHOD FOR BIASING PHASE CHANGE MEMORY ARRAY FOR RELIABLE WRITING
App. No. 11/040,262
→
FORMING NONVOLATILE PHASE CHANGE MEMORY CELL HAVING A REDUCED THERMAL CONTACT AREA
App. No. 11/040,465
→
WRITE-ONCE NONVOLATILE PHASE CHANGE MEMORY ARRAY
App. No. 11/040,256
→
Non-volatile memory cell comprising a dielectric layer and a phase change material in series
App. No. 11/040,255
→
DUAL-MODE DECODER CIRCUIT, INTEGRATED CIRCUIT MEMORY ARRAY INCORPORATING SAME, AND RELATED METHODS OF OPERATION
App. No. 11/026,493
→
INTEGRATED CIRCUIT INCLUDING MEMORY ARRAY INCORPORATING MULTIPLE TYPES OF NAND STRING STRUCTURES
App. No. 11/026,492
→
APPARATUS AND METHOD FOR HIERARCHICAL DECODING OF DENSE MEMORY ARRAYS USING MULTIPLE LEVELS OF MULTIPLE-HEADED DECODERS
App. No. 11/026,470
→
METHOD AND APPARATUS FOR IMPROVING YIELD IN SEMICONDUCTOR DEVICES BY GUARANTEEING HEALTH OF REDUNDANCY INFORMATION
App. No. 11/024,516
→
Solid-state memory device storing program code and methods for use therewith
App. No. 11/021,238
→
APPARATUS AND METHOD FOR MEMORY OPERATIONS USING ADDRESS-DEPENDENT CONDITIONS
App. No. 11/015,440
→
NONVOLATILE MEMORY CELL COMPRISING A REDUCED HEIGHT VERTICAL DIODE
App. No. 11/015,824
→
METHOD FOR CLEANING SLURRY PARTICLES FROM A SURFACE POLISHED BY CHEMICAL MECHANICAL POLISHING
App. No. 11/013,067
→
NAND MEMORY ARRAY INCORPORATING MULTIPLE WRITE PULSE PROGRAMMING OF INDIVIDUAL MEMORY CELLS AND METHOD FOR OPERATION OF SAME
PCTPCTUS2004040318
→
NAND MEMORY ARRAY INCORPORATING MULTIPLE SERIES SELECTION DEVICES AND METHOD FOR OPERATION OF SAME
PCTPCTUS2004040283
→
MANUFACTURING METHOD FOR INTEGRATED CIRCUIT HAVING DISTURB-FREE PROGRAMMING OF PASSIVE ELEMENT MEMORY CELLS
App. No. 10/994,020
→
APPARATUS AND METHOD FOR DISTURB-FREE PROGRAMMING OF PASSIVE ELEMENT MEMORY CELLS
App. No. 10/994,016
→
MEMORY DEVICE AND METHOD FOR SIMULTANEOUSLY PROGRAMMING AND/OR READING MEMORY CELLS ON DIFFERENT LEVELS
App. No. 10/987,091
→
TFT MASK ROM AND METHOD FOR MAKING SAME
App. No. 10/965,780
→
SEMICONDUCTOR DEVICE WITH LOCALIZED CHARGE STORAGE DIELECTRIC AND METHOD OF MAKING SAME
App. No. 10/965,763
→
Method and apparatus to control playback in a download-and-view video on demand system
App. No. 10/968,196
→
REDUNDANT MEMORY STRUCTURE USING BAD BIT POINTERS
App. No. 10/961,501
→
SYSTEM AND METHOD OF CONTROLLING A THREE-DIMENSIONAL MEMORY
App. No. 10/955,048
→
METHOD AND APPARATUS FOR USING A ONE-TIME OR FEW-TIME PROGRAMMABLE MEMORY WITH A HOST DEVICE DESIGNED FOR ERASABLE/REWRITEABLE MEMORY
App. No. 10/956,463
→
Method of programming a monolithic three-dimensional memory
App. No. 10/955,049
→
NONVOLATILE MEMORY CELL WITHOUT A DIELECTRIC ANTIFUSE HAVING HIGH- AND LOW-IMPEDANCE STATES
App. No. 10/955,549
→
Fuse memory cell comprising a diode, the diode serving as the fuse element
App. No. 10/955,387
→
DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS
App. No. 10/955,710
→
MEMORY CELL COMPRISING A SEMICONDUCTOR JUNCTION DIODE CRYSTALLIZED ADJACENT TO A SILICIDE
App. No. 10/954,510
→
JUNCTION DIODE COMPRISING VARYING SEMICONDUCTOR COMPOSITIONS
App. No. 10/954,577
→
LARGE-GRAIN P-DOPED POLYSILICON FILMS FOR USE IN THIN FILM TRANSISTORS
App. No. 10/936,168
→
NONSELECTIVE UNPATTERNED ETCHBACK TO EXPOSE BURIED PATTERNED FEATURES
App. No. 10/883,417
→
AN IMPROVED METHOD FOR MAKING CONTACTS IN A HIGH-DENISITY MEMORY
App. No. 10/855,785
→
A HIGH-DENSITY THREE-DIMENSIONAL MEMORY CELL
App. No. 10/855,784
→
METHOD FOR MAKING HIGH DENSITY NONVOLATILE MEMORY
App. No. 10/855,880
→
A HIGH-DENSITY THREE-DIMENSIONAL MEMORY
App. No. 10/855,778
→
METHOD FOR MAKING HIGH DENSITY NONVOLATILE MEMORY
App. No. 10/855,775
→
METHOD FOR MAKING HIGH DENSITY NONVOLATILE MEMORY
App. No. 10/855,804
→
RAIL STACK ARRAY OF CHARGE STORAGE DEVICES AND METHOD OF MAKING SAME
App. No. 10/849,000
→
TWO MASK FLOATING GATE EEPROM AND METHOD OF MAKING
App. No. 10/849,152
→
VERTICALLY STACKED, FIELD PROGRAMMABLE, NONVOLATILE MEMORY AND METHOD OF FABRICATION
App. No. 10/848,601
→
DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 10/842,008
→
THREE-DIMENSIONAL MEMORY DEVICE WITH ECC CIRCUITRY
App. No. 10/840,815
→
Photomask features with chromeless nonprinting phase shifting window
App. No. 10/815,312
→
THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED BIT LINE MEMORY ARRAY
PCTPCTUS2004009756
→
MULTIPLE-MODE MEMORY AND METHOD FOR FORMING SAME
App. No. 10/813,455
→
METHOD FOR PROGRAMMING A THREE-DIMENSIONAL MEMORY ARRAY INCORPORATING SERIAL CHAIN DIODE STACK
App. No. 10/809,146
→
CONFIGURING FILE STRUCTURES AND FILE SYSTEM STRUCTURES IN A MEMORY DEVICE
App. No. 10/806,826
→
THREE-DIMENSIONAL MEMORY ARRAY AND METHOD OF FABRICATION
App. No. 10/805,147
→