Doped polysilicon via connecting polysilicon layers
View Patent ↗The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.
1. A structure in a semiconductor device comprising:
a thin film channel layer in a first device level of thin film transistors, the first device level is at a first height above a substrate and comprises at least three series-connected thin film transistors having a plurality of shared source/drain regions; and
a polysilicon via in contact with the thin film channel layer, wherein the thin film channel layer is above the polysilicon via, a bottom end of the polysilicon via contacts one of the plurality of shared source/drain regions, and the polysilicon via has a dopant concentration greater than about 1×10 19 atoms/cm 3 .
2. The structure of claim 1 , wherein at least a second device level of thin film transistors exists above the first device level of thin film transistors, the second device level comprises at least three series-connected thin film transistors having a plurality of shared source/drain regions, the at least three series-connected thin film transistors of the second device level are vertically aligned with the at least three series-connected thin film transistors of the first device level.
3. The structure of claim 2 wherein the first and second device levels are vertically stacked in a monolithic three dimensional array.
4. The structure of claim 3 , wherein the plurality of charge storage memory cells comprise floating gate memory cells.
5. The structure of claim 2 , wherein a top end of the polysilicon via contacts one of the plurality of shared source/drain regions of the second device level.
6. The structure of claim 5 wherein the plurality of charge storage memory cells comprise SONOS-type memory cells.
7. The structure of claim 1 wherein the substrate comprises monocrystalline silicon.
8. A structure in a semiconductor device comprising:
a first channel layer, wherein the first channel layer is a portion of a first device level of thin film transistors, the first device level at a first height above a substrate, and the first device level of thin film transistors comprises a plurality of charge storage memory cells;
a second channel layer, wherein the second channel layer is a portion of a second device level of thin film transistors, the second device level at a second height above the substrate, wherein the second height is above the first height; and
a polysilicon via in contact with the first channel layer and in contact with the second channel layer, the polysilicon via has a first dopant concentration greater than about 1×10 19 atoms/cm 3 .
9. The structure of claim 8 wherein the first and second device levels are vertically stacked in a monolithic three dimensional array.
10. The structure of claim 8 , wherein the plurality of charge storage memory cells comprises SONOS-type memory cells.
11. The structure of claim 8 , wherein the plurality of charge storage memory cells comprises floating gate memory cells.
12. The structure of claim 8 wherein the substrate comprises monocrystalline silicon.
13. A structure in a semiconductor device comprising:
a substrate comprising monocrystalline silicon;
a dielectric insulating layer formed on the substrate;
a lower polysilicon layer formed above the substrate, on the dielectric insulating layer;
a polysilicon via above the lower polysilicon layer, the polysilicon via having a top end and a bottom end, wherein the bottom end of the polysilicon via is in contact with the lower polysilicon layer; and
an upper polysilicon layer above the polysilicon via, wherein the top end of the polysilicon via is in contact with the upper polysilicon layer, the lower polysilicon layer is a portion of a channel layer of a first thin film transistor, the upper polysilicon layer is a portion of a channel layer of a second thin film transistor, the channel layer of the first thin film transistor is a portion of a first device level formed at a first height above the substrate, the channel layer of the second thin film transistor is a portion of a second device level formed at a second height above the substrate, the second height is above the first height, the second device level is monolithically formed above the first device level in a monolithic three dimensional array, and the monolithic three dimensional array comprises a plurality of memory cells.
14. The structure of claim 13 , wherein the plurality of memory cells comprise charge storage memory cells.
15. The structure of claim 14 wherein the charge storage memory cells are SONOS-type memory cells.
16. A structure in a semiconductor device comprising:
a lower polysilicon layer;
a polysilicon via above the lower polysilicon layer, the polysilicon via having a top end and a bottom end, wherein the bottom end of the polysilicon via is in contact with the lower polysilicon layer; and
an upper polysilicon layer above the polysilicon via, wherein the top end of the polysilicon via is in contact with the upper polysilicon layer, the polysilicon via has a first dopant concentration and the upper and/or lower polysilicon layer has a second dopant concentration, wherein the first dopant concentration is at least two orders of magnitude higher than the second dopant concentration.
17. A structure in a semiconductor device comprising:
a first channel layer, wherein the first channel layer is a portion of a first device level of series-connected thin film transistors having a plurality of common source/drain regions, the first device level at a first height above a substrate;
a second channel layer, wherein the second channel layer is a portion of a second device level of series-connected thin film transistors having a plurality of common source/drain regions, the second device level at a second height above the substrate, wherein the second height is above the first height; and
a polysilicon via in contact with the first channel layer and in contact with the second channel layer, a bottom end of the polysilicon via contacts a top end of one of the plurality of common source/drain regions of the first device level, a top end of the polysilicon via contacts a bottom end of one of the plurality of common source/drain regions of the second device level, and the second channel layer has a second dopant concentration less than about 1×10 17 atoms/cm 3 .