Patent Assignment
Reel/Frame 038520/0552
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT LISTED PATENT NUMBER 8853569 TO THE CORRECT PATENT NUMBER 8883569 PREVIOUSLY RECORDED ON REEL 038300 FRAME 0665. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.
Recorded: 2016-04-25
Received: 2016-04-25
Pages: 162
Assignor
SANDISK 3D LLC
Executed: 2016-03-24
Assignee
SANDISK TECHNOLOGIES INC.
TWO LEGACY TOWN CENTER 6900 NORTH DALLAS PARKWAY, PLANO, TX, 75024, UNITED STATES
Covered Applications
(100)
MULTI-LEVEL REVERSIBLE RESISTANCE-SWITCHING MEMORY
App. No. 15/049,088
→
WORD LINE COMPENSATION FOR MEMORY ARRAYS
App. No. 15/015,672
→
LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE
App. No. 14/996,144
→
MONOLITHIC THREE DIMENSIONAL MEMORY ARRAYS FORMED USING SACRIFICIAL POLYSILICON PILLARS
App. No. 14/995,224
→
DATA-PATH CONTROL WITH INTERNAL CLOCK AND ASYNCHRONOUS FIFO
App. No. 62/278,227
→
Vertical Bit Line Non-Volatile Memory Systems And Methods Of Fabrication
App. No. 14/938,637
→
THREE-DIMENSIONAL ARRAY OF RE-PROGRAMMABLE NON-VOLATILE MEMORY ELEMENTS HAVING VERTICAL BIT LINES
App. No. 14/933,672
→
RERAM MIM STRUCTURE FORMATION
App. No. 14/928,999
→
RESISTIVE RANDOM ACCESS MEMORY CONTAINING A STEERING ELEMENT AND A TUNNELING DIELECTRIC ELEMENT
App. No. 14/924,144
→
Scan Chain Circuits In Non-Volatile Memory
App. No. 14/919,154
→
TIMED MULTIPLEX SENSING
App. No. 14/887,547
→
MULTIPLE LAYER FORMING SCHEME FOR VERTICAL CROSS POINT RERAM
App. No. 14/887,532
→
MEMORY CELLS INCLUDING VERTICALLY ORIENTED ADJUSTABLE RESISTANCE STRUCTURES
App. No. 14/869,231
→
DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 14/856,131
→
THREE-DIMENSIONAL RESISTIVE RANDOM ACCESS MEMORY CONTAINING SELF-ALIGNED MEMORY ELEMENTS
App. No. 14/851,296
→
Resistance-Switching Memory Cell With Multiple Raised Structures In A Bottom Electrode
App. No. 14/807,370
→
DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME
App. No. 14/804,126
→
Silicided Bit Line For Reversible-Resistivity Memory
App. No. 14/795,211
→
VERTICAL BIT LINE WIDE BAND GAP TFT DECODER
App. No. 14/793,167
→
THREE DIMENSIONAL NON-VOLATILE STORAGE WITH CONNECTED WORD LINES
App. No. 14/746,003
→
VERTICAL CROSS POINT RERAM FORMING METHOD
App. No. 14/732,766
→
Multiple Junction Thin Film Transistor
App. No. 14/723,038
→
SIDE WALL BIT LINE STRUCTURES
App. No. 14/716,382
→
AUTO-TRACKING UNSELECTED WORD LINE VOLTAGE GENERATOR
App. No. 14/716,388
→
REDUCING DISTURB WITH ADJUSTABLE RESISTANCE BIT LINE STRUCTURES
App. No. 14/715,586
→
SETTING CHANNEL VOLTAGES OF ADJUSTABLE RESISTANCE BIT LINE STRUCTURES USING DUMMY WORD LINES
App. No. 14/715,579
→
CONTROLLING ADJUSTABLE RESISTANCE BIT LINES CONNECTED TO WORD LINE COMBS
App. No. 14/715,583
→
OPERATION MODES FOR ADJUSTABLE RESISTANCE BIT LINE STRUCTURES TO REDUCE LEAKAGE CURRENTS THROUGH UNSELECTED MEMORY CELLS
App. No. 14/715,575
→
INTRINSIC VERTICAL BIT LINE ARCHITECTURE
App. No. 14/715,562
→
MEMORY HOLE BIT LINE STRUCTURES
App. No. 14/715,566
→
NON-VOLATILE STORAGE SYSTEM BIASING CONDITIONS FOR STANDBY AND FIRST READ
App. No. 14/700,134
→
Vertical Bit Line Non-Volatile Memory With Recessed Word Lines
App. No. 14/681,398
→
Sense Amplifier With Integrating Capacitor And Methods Of Operation
App. No. 14/663,775
→
Leakage Current Compensation With Reference Bit Line Sensing In Non-Volatile Memory
App. No. 14/663,786
→
MULTILEVEL CONTACT TO A 3D MEMORY ARRAY AND METHOD OF MAKING THEREOF
App. No. 14/643,211
→
PARALLEL BIT LINE THREE-DIMENSIONAL RESISTIVE RANDOM ACCESS MEMORY
App. No. 14/635,419
→
Floating Staircase Word Lines and Process in a 3D Non-Volatile Memory Having Vertical Bit Lines
App. No. 14/631,616
→
VERTICAL TRANSISTOR AND LOCAL INTERCONNECT STRUCTURE
App. No. 14/623,843
→
INDEPENDENT SENSE AMPLIFIER ADDRESSING AND QUOTA SHARING IN NON-VOLATILE MEMORY
App. No. 14/619,985
→
Method Of Operating FET Low Current 3D Re-Ram
App. No. 14/591,546
→
INDEPENDENT SET/RESET PROGRAMMING SCHEME
App. No. 14/547,473
→
MEMORY ARRAY HAVING DIVIDED APART BIT LINES AND PARTIALLY DIVIDED BIT LINE SELECTOR SWITCHES
App. No. 14/543,690
→
MONOLITHIC THREE DIMENSIONAL MEMORY ARRAYS WITH STAGGERED VERTICAL BIT LINE SELECT TRANSISTORS AND METHODS THERFOR
App. No. 14/542,213
→
SENSE AMPLIFIER INCLUDING A SINGLE-TRANSISTOR AMPLIFIER AND LEVEL SHIFTER AND METHODS THEREFOR
App. No. 14/539,150
→
HIGH ENDURANCE NON-VOLATILE STORAGE
App. No. 14/538,763
→
CONCAVE WORD LINE AND CONVEX INTERLAYER DIELECTRIC FOR PROTECTING A READ/WRITE LAYER
App. No. 14/529,731
→
CONCAVE WORD LINE AND CONVEX INTERLAYER DIELECTRIC FOR PROTECTING A READ/WRITE LAYER
App. No. 14/529,624
→
SINGLE-STAGE FOLDED CASCODE BUFFER AMPLIFIERS WITH ANALOG COMPARATORS
App. No. 14/522,678
→
MONOLITHIC THREE DIMENSIONAL MEMORY ARRAYS WITH STAGGERED VERTICAL BIT LINES AND DUAL-GATE BIT LINE SELECT TRANSISTORS
App. No. 14/522,777
→
DUAL GATE STRUCTURE
App. No. 14/519,068
→
Regrouping and Skipping Cycles in Non-Volatile Memory
App. No. 14/515,387
→
Vertical TFT With Tunnel Barrier
App. No. 14/515,054
→
CONTENT ADDRESSABLE MEMORY CELLS, MEMORY ARRAYS AND METHODS OF FORMING THE SAME
App. No. 14/512,552
→
Sensing Multiple Reference Levels In Non-Volatile Storage Elements
App. No. 14/508,615
→
COMPENSATION SCHEME FOR NON-VOLATILE MEMORY
App. No. 14/506,607
→
COMPENSATION SCHEME FOR NON-VOLATILE MEMORY
App. No. 14/506,610
→
METHODS AND APPARATUS FOR VERTICAL CROSS POINT RE-RAM ARRAY BIAS CALIBRATION
App. No. 14/502,093
→
APPARATUS AND METHODS FOR SENSING HARD BIT AND SOFT BITS
App. No. 14/500,476
→
DUAL CAPACITOR SENSE AMPLIFIER AND METHODS THEREFOR
App. No. 14/499,717
→
DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 14/494,320
→
WORD LINE CONNECTION FOR MEMORY DEVICE AND METHOD OF MAKING THEREOF
App. No. 14/463,113
→
METHODS AND SYSTEMS TO REDUCE LOCATION-BASED VARIATIONS IN SWITCHING CHARACTERISTICS OF 3D RERAM ARRAYS
App. No. 14/462,374
→
MULTI-LEVEL MEMORY ARRAYS WITH MEMORY CELLS THAT EMPLOY BIPOLAR STORAGE ELEMENTS AND METHODS OF FORMING THE SAME
App. No. 14/456,158
→
FULLY ISOLATED SELECTOR FOR MEMORY DEVICE
App. No. 14/451,664
→
SEMICONDUCTOR MEMORY DEVICE HAVING UNEQUAL PITCH VERTICAL CHANNEL TRANSISTORS USED AS SELECTION TRANSISTORS
App. No. 14/449,417
→
INTERLEAVED GROUPED WORD LINES FOR THREE DIMENSIONAL NON-VOLATILE STORAGE
App. No. 14/341,519
→
SHARED-GATE VERTICAL-TFT FOR VERTICAL BIT LINE ARRAY
App. No. 14/340,454
→
NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS WITH VERTICAL BIT LINES AND SELECT DEVICES AND METHODS THEREOF
App. No. 14/339,895
→
METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING
App. No. 14/334,653
→
REDUCING DISTURBANCES IN MEMORY CELLS
App. No. 14/324,259
→
MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME
App. No. 14/299,240
→
Charge Pump System That Dynamically Selects Number of Active Stages
App. No. 14/291,481
→
THREE DIMENSIONAL HEXAGONAL MATRIX MEMORY ARRAY
App. No. 14/291,415
→
METHODS AND APPARATUS FOR REDUCING PROGRAMMING TIME OF A MEMORY CELL
App. No. 14/290,888
→
CONTINUOUS PROGRAMMING OF NON-VOLATILE MEMORY
App. No. 14/290,934
→
Page Buffer Program Command And Methods To Reprogram Pages Without Re-Inputting Data To A Memory Device
App. No. 14/285,829
→
SENSE AMPLIFIER LOCAL FEEDBACK TO CONTROL BIT LINE VOLTAGE
App. No. 14/283,034
→
THREE-DIMENSIONAL NONVOLATILE MEMORY AND METHOD OF FABRICATION
App. No. 14/270,409
→
THREE DIMENSIONAL NON-VOLATILE STORAGE WITH ASYMMETRICAL VERTICAL SELECT DEVICES
App. No. 14/269,107
→
Charge Pump with a Power-Controlled Clock Buffer to Reduce Power Consumption and Output Voltage Ripple
App. No. 14/258,934
→
TEMPERATURE COMPENSATION OF CONDUCTIVE BRIDGE MEMORY ARRAYS
App. No. 14/256,925
→
COMPENSATION SCHEME FOR NON-VOLATILE MEMORY
App. No. 14/254,883
→
LOAD AND SHORT CURRENT MEASUREMENT BY CURRENT SUMMATION TECHNIQUE
App. No. 14/254,880
→
LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT
App. No. 14/249,628
→
VERTICAL CROSS POINT RERAM FORMING METHOD
App. No. 14/246,052
→
MULTIPLE LAYER FORMING SCHEME FOR VERTICAL CROSS POINT RERAM
App. No. 14/246,053
→
Method for Improving the Precision of a Temperature-Sensor Circuit
App. No. 14/242,623
→
Memory Device with Improved Temperature-Sensor Circuit
App. No. 14/242,632
→
PROGRAM CYCLE SKIP
App. No. 14/231,591
→
NON-VOLATILE 3D MEMORY WITH CELL-SELECTABLE WORD LINE DECODING
App. No. 14/229,482
→
DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 14/227,644
→
DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 14/227,425
→
TRANSISTOR DEVICE WITH GATE BOTTOM ISOLATION AND METHOD OF MAKING THEREOF
App. No. 14/224,290
→
NON-VOLATILE STORAGE SYSTEM USING OPPOSITE POLARITY PROGRAMMING SIGNALS FOR MIM MEMORY CELL
App. No. 14/216,251
→
DUAL CHANNEL VERTICAL FIELD EFFECT TRANSISTOR INCLUDING AN EMBEDDED ELECTRODE
App. No. 14/206,196
→
NON-VOLATILE STORAGE SYSTEM WITH DUAL BLOCK PROGRAMMING
App. No. 14/201,899
→
Vertical Thin Film Transistor Selection Devices And Methods Of Fabrication
App. No. 14/197,985
→
PLASMA REDUCTION METHOD FOR MODIFYING METAL OXIDE STOICHIOMETRY IN RERAM
App. No. 14/196,647
→
NON-VOLATILE STORAGE SYSTEM BIASING CONDITIONS FOR STANDBY AND FIRST READ
App. No. 14/197,136
→
Vertical Bit Line Non-Volatile Memory Systems And Methods Of Fabrication
App. No. 14/196,904
→