IP Library Granted Patent US 9,576,673
Granted Patent B2
US 9,576,673 · App. 14/508,615 · Granted Feb 21, 2017

Sensing multiple reference levels in non-volatile storage elements

Inventors: Xiaowei Jiang (San Jose, CA); Chang Siau (Saratoga, CA); Siu Lung Chan (Santa Clara, CA)
Assignee: SanDisk Technologies LLC
G11C16/28G11C11/5642G11C16/0466G11C16/0483G11C16/26G11C16/3459G11C2211/5621
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Quick Facts
Patent No.
US 9,576,673
App. No.
14/508,615
Granted
Feb 21, 2017
Kind
B2
Abstract

Disclosed herein are techniques for sensing multiple reference levels in non-volatile storage elements without changing the voltage on the selected word line. One aspect includes determining a first condition of a selected non-volatile storage element with respect to a first reference level based on whether a sensing transistor conducts in response to a sense voltage on a sense node. Then, a voltage on the source terminal of the sensing transistor is modified after determining the first condition with respect to the first reference level. A second condition of the selected non-volatile storage element is then determined with respect to a second reference level based on whether the sensing transistor conducts in response to the sense voltage on the sense node. This allows two different reference levels to be efficiently sensed. Dynamic power is saved due low capacitance of the sensing transistor relative to the sense node.

Claims (56)

1. A non-volatile storage device, comprising:

a selected non-volatile storage element;

a charge storage device coupled to the selected non-volatile storage element and a sensing device having a control terminal coupled to the charge storage device,

a pre-charge circuit and bit line connection circuit configured to develop a sense voltage on the charge storage device in response to a signal from a state machine, the sense voltage is developed based on connecting the selected non-volatile storage element to the charge storage device for a sense time;

a processor configured to determine whether the sensing device activates in response to the sense voltage that was developed on the charge storage device based on connecting the selected non-volatile storage element to the charge storage device for the sense time;

the processor further configured to determine a first condition of the selected non-volatile storage element with respect to a first reference level based on whether the sensing device activates in response to the sense voltage developed on the charge storage device,

a voltage supply configured to modify a voltage on a second terminal of the sensing device other than the control terminal after determining the first condition in response to a signal from the state machine;

the processor configured to determine whether the sensing device activates after modifying the voltage on the second terminal in response to the sense voltage that was developed on the charge storage device based on connecting the selected non-volatile storage element to the charge storage device for the sense time,

the processor configured to determine a second condition of the selected non-volatile storage element with respect to a second reference level based on whether the sensing device activates in response to the sense voltage developed on the charge storage device after modifying the voltage on the second terminal of the sensing device.

2. The non-volatile storage device of claim 1 , wherein the bit line connection circuit is configured to connect the charge storage device to a bit line for the sense time to allow a current from the bit line to discharge the charge storage device for the sense time.

3. The non-volatile storage device of claim 1 , wherein the voltage supply increases a voltage on the second terminal in response to a signal from the state machine in order to modify the voltage on the second terminal.

4. The non-volatile storage device of claim 1 , wherein the pre-charge circuit is configured to modify a voltage on the charge storage device after the first condition of the selected non-volatile storage element is determined with respect to the first reference level, the processor is configured to determine whether the sensing device activates in response to the modified voltage on the charge storage device, the processor is configured to determine a third condition of the selected non-volatile storage element with respect to a third reference level based on whether the sensing device activates in response to the modified voltage on the charge storage device, the voltage supply is configured to modify the voltage on the second terminal of the sensing device after it is determined whether the sensing device activates in response to the modified voltage on the charge storage device, the third reference level being between the first reference level and the second reference level.

5. The non-volatile storage device of claim 1 , further comprising a data latch that stores a first result in response to whether the sensing device activates in response to the sense voltage on the charge storage device prior to modifying the voltage on the second terminal of the sensing device, the first result indicates whether the selected non-volatile storage element has a threshold voltage above or below a first target threshold voltage, the data latch stores a second result in response to whether the sensing device activates in response to the sense voltage on the charge storage device after modifying the voltage on the second terminal of the sensing device, the second result indicates whether the selected non-volatile storage element has a threshold voltage above or below a second target threshold voltage.

6. The non-volatile storage device of claim 1 , wherein when the pre-charge circuit and bit line connection circuit develop the sense voltage on the charge storage device the voltage supply applies a voltage to a word line associated with the selected non-volatile storage element in response to a signal from the state machine.

7. The non-volatile storage device of claim 1 , wherein the selected non-volatile storage element is part of a 3D memory array.

8. The non-volatile storage device of claim 1 , wherein the selected non-volatile storage element comprises a charge trapping region that store data.

9. The non-volatile storage device of claim 1 , wherein the sensing device comprises a transistor having a source terminal, wherein the second terminal is the source terminal.

10. A method comprising:

developing a sense voltage on a sense node connected to a sensing device, including connecting the sense node to a selected non-volatile storage element to discharge the sense node for a sense time;

determining a first condition of the selected non-volatile storage element with respect to a first reference level based on whether the sensing device activates in response to the sense voltage that was developed on the sense node based on discharging the sense node for the sense time;

modifying a voltage on a node of the sensing device after determining the first condition with respect to the first reference level; and

determining a second condition of the selected non-volatile storage element with respect to a second reference level based on whether the sensing device activates after modifying the voltage on the node of the sensing device in response to the sense voltage that was developed on the sense node based on discharging the sense node for the sense time.

11. The method of claim 10 , wherein the modifying a voltage on the node of the sensing device comprises:

increasing a voltage on the sense node of the sensing device.

12. The method of claim 10 , wherein the developing a sense voltage on a sense node comprises:

charging the sense node;

connecting the sense node to a bit line that is associated with the selected non-volatile storage element; and

allowing a current from the bit line to discharge the sense node for the sense time.

13. The method of claim 10 , further comprising:

modifying a voltage on the sense node after determining the first condition of the selected non-volatile storage element with respect to the first reference level;

determining whether the sensing device activates in response to the modified voltage on the sense node prior to modifying the voltage on the node of the sensing device; and

determining a third condition of the selected non-volatile storage element with respect to a third reference level based on whether the sensing device activates in response to the modified voltage on the sense node prior to modifying the voltage on the node of the sensing device, wherein the modifying a voltage on a node of the sensing device is performed after determining whether the sensing device activates in response to the modified voltage on the sense node, the third reference level being between the first reference level and the second reference level.

14. The method of claim 10 , wherein the first reference level is whether the selected non-volatile storage element has a threshold voltage above or below a first threshold voltage, wherein the second reference level is whether the selected non-volatile storage element has a threshold voltage above or below a second threshold voltage.

15. The method of claim 10 , further comprising:

applying a voltage to a word line associated with the selected non-volatile storage element;

wherein connecting the sense node to the selected non-volatile storage element to discharge the sense node for the sense time comprises allowing current from a bit line associated with the selected non-volatile storage element that results from applying the voltage to the word line to discharge the sense node for the sense time.

16. The method of claim 10 , wherein the first reference level is a low verify level for a state and the second reference level is a high verify level for the same state.

17. The method of claim 10 , wherein the sensing device is a sensing transistor comprising a source terminal, wherein modifying the voltage on the node of the sensing device comprises modifying a voltage on the source terminal of the sensing transistor.

18. A 3D non-volatile storage device comprising:

a plurality of word line layers;

a plurality of insulator layers alternating with the word line layers in a stack;

a plurality of non-volatile storage element strings, each non-volatile storage element string comprises a plurality of non-volatile storage elements, each of the non-volatile storage elements is associated with one of the plurality of word line layers;

a plurality of bit lines associated with the non-volatile storage element strings;

a plurality of sensing circuits each comprising a sense node and a sensing transistor connected to the sense node; and

managing circuitry in communication with the plurality of word line layers, the plurality of bit lines, the plurality of strings, and the plurality of sensing circuits, wherein the managing circuitry develops a sense voltage on the sense node of a given sensing circuit, the given sensing circuit being associated with a first bit line of the bit lines, the first bit line being associated with a selected non-volatile storage element of the plurality of non-volatile storage elements, wherein the managing circuitry determines whether the sensing transistor in the given sensing circuit conducts in response to the sense voltage on the sense node, wherein the managing circuitry determines a condition of the selected non-volatile storage element with respect to a first level based on whether the sensing transistor conducts in response to the sense voltage on the sense node, wherein the managing circuitry modifies a voltage on a source terminal of the sensing transistor after determining the condition with respect to the first level, wherein the managing circuitry determines whether the sensing transistor conducts in response to the sense voltage on the sense node after modifying the voltage on the source terminal of the sensing transistor, wherein the managing circuitry determines a condition of the selected non-volatile storage element with respect to a second level based on whether the sensing transistor conducts in response to the sense voltage on the sense node after modifying the voltage on the source terminal of the sensing transistor.

19. A method of operating non-volatile storage, the method comprising:

a) developing a sense voltage on a sense capacitor that is coupled to a bit line, the sense capacitor having a bottom plate and a top plate, wherein the sense capacitor is connected to a sensing transistor having a source terminal, wherein a selected non-volatile storage element is associated with the bit line;

b) determining whether the sensing transistor conducts in response to the sense voltage on the top plate of the sense capacitor;

c) reducing a voltage on the bottom plate of the sense capacitor after determining whether the sensing transistor conducts in response to the sense voltage on the sense capacitor;

d) determining whether the sensing transistor conducts in response to the sense voltage on the top plate of the sense capacitor after boosting the voltage on the bottom plate of the sense capacitor;

e) increasing a voltage on the source terminal of the sensing transistor after determining whether the sensing transistor conducts after boosting the voltage on the bottom plate;

f) determining whether the sensing transistor conducts in response to the sense voltage on the top plate of the sense capacitor after increasing the voltage on the source terminal of the sensing transistor; and

g) detecting conditions of the selected non-volatile storage element with respect to a first reference level, a second reference level, and a third reference level based on whether the sensing transistor conducted in said b), said d) and said f), respectively.

20. The method of claim 19 , wherein the developing a sense voltage on a sense capacitor that is coupled to a bit line comprises:

causing the selected non-volatile storage element to create a current in the bit line; and

discharging the sense capacitor for a sense time.

Assignments (4)
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038807/0807 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT LISTED PATENT NUMBER 8853569 TO THE CORRECT PATENT NUMBER 8883569 PREVIOUSLY RECORDED ON REEL 038300 FRAME 0665. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 25, 2016
From: SANDISK 3D LLC
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038520/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2016
From: SANDISK 3D LLC.
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038300/0665 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2014
From: JIANG, XIAOWEI; SIAU, CHANG; CHAN, SIU LUNG
To: SANDISK 3D LLC
Reel/Frame 034211/0042 →
Continuity (1)
Related Publication 20160099070A1 · Apr 7, 2016