Patent Assignment
Reel/Frame 038807/0807
CHANGE OF NAME
Recorded: 2016-05-25
Received: 2016-05-25
Pages: 18
Assignor
SANDISK TECHNOLOGIES INC
Executed: 2016-05-16
Assignee
SANDISK TECHNOLOGIES LLC
6900 DALLAS PARKWAY, SUITE 325, PLANO, TX, 75024, UNITED STATES
Covered Applications
(100)
Digitally Controlled Source Side Select Gate Offset in 3D NAND Memory Erase
App. No. 14/667,014
→
Host System and Process to Reduce Declared Capacity of a Storage Device by Trimming
App. No. 14/621,135
→
SELF-ALIGNED INTEGRATED LINE AND VIA STRUCTURE FOR A THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
App. No. 14/620,593
→
SPACER PASSIVATION FOR HIGH-ASPECT RATIO OPENING FILM REMOVAL AND CLEANING
App. No. 14/620,674
→
TRIGGERING A PROCESS TO REDUCE DECLARED CAPACITY OF A STORAGE DEVICE
App. No. 14/621,200
→
Process and Apparatus to Reduce Declared Capacity of a Storage Device by Moving Data
App. No. 14/621,121
→
Process and Apparatus to Reduce Declared Capacity of a Storage Device by Deleting Data
App. No. 14/621,107
→
Process and Apparatus to Reduce Declared Capacity of a Storage Device by Altering an Encoding Format
App. No. 14/621,212
→
Triggering, at a Host System, a Process to Reduce Declared Capacity of a Storage Device
App. No. 14/621,219
→
RESISTANCE-BASED MEMORY WITH AUXILIARY REDUNDANCY INFORMATION
App. No. 14/620,753
→
Process and Apparatus to Reduce Declared Capacity of a Storage Device by Trimming
App. No. 14/621,090
→
SAFE MODE BOOT LOADER
App. No. 14/619,486
→
INDEPENDENT SENSE AMPLIFIER ADDRESSING AND QUOTA SHARING IN NON-VOLATILE MEMORY
App. No. 14/619,985
→
ENHANCED CHANNEL MOBILITY THREE-DIMENSIONAL MEMORY STRUCTURE AND METHOD OF MAKING THEREOF
App. No. 14/619,691
→
Adaptive Data Shaping in Nonvolatile Memory
App. No. 14/618,317
→
SENSE AMPLIFIER WITH EFFICIENT USE OF DATA LATCHES
App. No. 14/616,289
→
STATE-DEPENDENT LOCKOUT IN NON-VOLATILE MEMORY
App. No. 14/616,309
→
Memory System and Method for Power-Based Operation Scheduling
App. No. 14/616,376
→
Process for Forming Wide and Narrow Conductive Lines
App. No. 14/616,219
→
MEMORY DEVICE WITH COMB- SHAPED ELECTRODE HAVING A PLURALITY OF ELECTRODE FINGERS AND METHOD OF MAKING THEREOF
App. No. 14/614,709
→
Memory Block Allocation By Block Health
App. No. 14/613,718
→
COBALT-CONTAINING CONDUCTIVE LAYERS FOR CONTROL GATE ELECTRODES IN A MEMORY STRUCTURE
App. No. 14/613,956
→
ADJUSTABLE READ TIME FOR MEMORY
App. No. 14/613,216
→
MODEL BASED CONFIGURATION PARAMETER MANAGEMENT
App. No. 14/612,282
→
SYSTEM, METHOD, AND APPARATUS FOR IMPROVING THE UTILITY OF STORAGE MEDIA
App. No. 14/611,088
→
Immediate Feedback Before or During Programming
App. No. 14/607,408
→
ADAPTIVE MULTI-PAGE PROGRAMMING METHODS AND APPARATUS FOR NON-VOLATILE MEMORY
App. No. 14/602,468
→
COMPOSITE CONTACT VIA STRUCTURE CONTAINING AN UPPER PORTION WHICH FILLS A CAVITY WITHIN A LOWER PORTION
App. No. 14/602,491
→
META PLANE OPERATIONS FOR A STORAGE DEVICE
App. No. 14/603,071
→
CONFIGURATION PARAMETER MANAGEMENT FOR NON-VOLATILE DATA STORAGE
App. No. 14/601,794
→
DISTRIBUTING STORAGE OF ECC CODE WORDS
App. No. 14/601,806
→
Method Of Reducing Hot Electron Injection Type Of Read Disturb In Memory
App. No. 14/601,531
→
SYSTEMS AND METHODS FOR GENERATING HINT INFORMATION ASSOCIATED WITH A HOST COMMAND
App. No. 14/601,350
→
System, Method and Apparatus to Relieve Stresses in a Semiconductor Wafer Caused by Uneven Internal Metallization Layers
App. No. 14/600,320
→
SEMICONDUCTOR STRUCTURE WITH CONCAVE BLOCKING DIELECTRIC SIDEWALL AND METHOD OF MAKING THEREOF BY ISOTROPICALLY ETCHING THE BLOCKING DIELECTRIC LAYER
App. No. 14/600,226
→
Method And Apparatus For Refresh Programming Of Memory Cells Based On Amount Of Threshold Voltage Downshift
App. No. 14/600,365
→
CONFIGURATION PARAMETER MANAGEMENT USING A CONFIGURATION TOOL
App. No. 14/601,226
→
INITIALIZATION TECHNIQUES FOR MULTI-LEVEL MEMORY CELLS USING MULTI-PASS PROGRAMMING
App. No. 14/600,675
→
Selective Online Burn-In with Adaptive and Delayed Verification Methods for Memory
App. No. 14/600,342
→
System, Method and Apparatus to Relieve Stresses in a Semiconductor Die Caused by Uneven Internal Metallization Layers
App. No. 14/600,316
→
Suspending and Resuming Non-Volatile Memory Operations
App. No. 14/599,183
→
METHOD AND DEVICE FOR DISTRIBUTING HOLDUP ENERGY TO MEMORY ARRAYS
App. No. 14/599,150
→
METHODS AND SYSTEMS FOR FLASH BUFFER SIZING
App. No. 14/599,168
→
DYNAMIC STORAGE CHANNEL
App. No. 14/599,267
→
DETECTING VOLTAGE THRESHOLD DRIFT
App. No. 14/599,240
→
Methods and Systems for Scalable and Distributed Address Mapping Using Non-Volatile Memory Modules
App. No. 14/597,167
→
Methods and Systems for Efficient Non-Isolated Transactions
App. No. 14/597,174
→
Methods and Systems for Scalable Reliability Management of Non-Volatile Memory Modules
App. No. 14/597,161
→
NON-VOLATILE MEMORY MODULE WITH PHYSICAL-TO-PHYSICAL ADDRESS REMAPPING
App. No. 14/597,169
→
Bulk Driven Low Swing Driver
App. No. 14/596,772
→
Methods and Systems for Insert Optimization of Tiered Data Structures
App. No. 14/597,181
→
MULTI-CLOCK GENERATION THROUGH PHASE LOCKED LOOP (PLL) REFERENCE
App. No. 14/596,779
→
Atomic Non-Volatile Memory Data Transfer
App. No. 14/596,181
→
Validating the Status of Memory Operations
App. No. 14/596,182
→
Electronic Assembly with Thermal Channel and Method of Manufacture Thereof
App. No. 14/596,176
→
COMPACTION PROCESS FOR A DATA STORAGE DEVICE
App. No. 14/595,897
→
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING PLURAL SELECT GATE TRANSISTORS HAVING DIFFERENT CHARACTERISTICS AND METHOD OF MAKING THEREOF
App. No. 14/595,572
→
Methods and Systems for Die Failure Testing
App. No. 14/596,177
→
SYSTEM AND METHOD FOR MEMORY COMMAND QUEUE MANAGEMENT AND CONFIGURABLE MEMORY STATUS CHECKING
App. No. 14/595,878
→
Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation
App. No. 14/595,553
→
Storage Module and Method for On-Chip Copy Gather
App. No. 14/595,939
→
SELECTIVE ECC REFRESH FOR ON DIE BUFFERED NON-VOLATILE MEMORY
App. No. 14/593,965
→
SELECTIVE COPYBACK FOR ON DIE BUFFERED NON-VOLATILE MEMORY
App. No. 14/593,938
→
NON-VOLATILE MEMORY HAVING INDIVIDUALLY OPTIMIZED SILICIDE CONTACTS AND PROCESS THEREFOR
App. No. 14/593,694
→
Conductive Lines with Protective Sidewalls
App. No. 14/593,528
→
Method Of Operating FET Low Current 3D Re-Ram
App. No. 14/591,546
→
Method and System for Using Non-Volatile Memory as a Replacement for Volatile Memory
App. No. 14/586,205
→
METHOD OF MAKING A VERTICAL NAND DEVICE USING SEQUENTIAL ETCHING OF MULTILAYER STACKS
App. No. 14/585,912
→
METHODS FOR MAKING A TRIM-RATE TOLERANT SELF-ALIGNED CONTACT VIA STRUCTURE ARRAY
App. No. 14/584,179
→
Non-Volatile Memory Systems Utilizing Storage Address Tables
App. No. 14/584,315
→
Systems and Methods for Choosing a Memory Block for the Storage of Data Based on a Frequency With Which the Data is Updated
App. No. 14/584,388
→
Ring Bus Architecture for Use in a Memory Module
App. No. 14/584,358
→
System and Method for Utilizing History Information in a Memory Device
App. No. 14/584,825
→
EFFICIENT SCANNING OF NONVOLATILE MEMORY BLOCKS
App. No. 14/581,748
→
System and Method for Selecting Blocks for Garbage Collection Based on Block Health
App. No. 14/581,551
→
THREE DIMENSIONAL NAND MEMORY HAVING IMPROVED CONNECTION BETWEEN SOURCE LINE AND IN-HOLE CHANNEL MATERIAL AS WELL AS REDUCED DAMAGE TO IN-HOLE LAYERS
App. No. 14/579,608
→
NONVOLATILE MEMORY SYSTEM STORING SYSTEM DATA IN MARGINAL WORD LINES
App. No. 14/577,239
→
Time Domain Ramp Rate Control for Erase Inhibit in Flash Memory
App. No. 14/574,832
→
Fabricating 3D NAND Memory Having Monolithic Crystalline Silicon Vertical NAND Channel
App. No. 14/575,937
→
SYSTEM AND METHOD FOR ADAPTIVE MEMORY LAYERS IN A MEMORY DEVICE
App. No. 14/573,959
→
TEMPERATURE DEPENDENT SENSING SCHEME TO COUNTERACT CROSS-TEMPERATURE THRESHOLD VOLTAGE DISTRIBUTION WIDENING
App. No. 14/574,110
→
SYSTEM AND METHOD FOR MANAGING DATA IN A MEMORY DEVICE
App. No. 14/573,949
→
WORD LINE DEPENDENT TEMPERATURE COMPENSATION SCHEME DURING SENSING TO COUNTERACT CROSS-TEMPERATURE EFFECT
App. No. 14/574,114
→
Storage System Power Management Using Controlled Execution of Pending Memory Commands
App. No. 14/572,633
→
Throttling Command Execution in Non-Volatile Memory Systems Based on Power Usage
App. No. 14/572,619
→
Contact For Vertical Memory With Dopant Diffusion Stopper And Associated Fabrication Method
App. No. 14/572,146
→
TAG-BASED WEAR LEVELING FOR A DATA STORAGE DEVICE
App. No. 14/572,693
→
SELECTIVE BLOCKING DIELECTRIC FORMATION IN A THREE-DIMENSIONAL MEMORY STRUCTURE
App. No. 14/571,824
→
GENERALIZED STORAGE VIRTUALIZATION INTERFACE
App. No. 14/569,382
→
METHOD TO RECOVER CYCLING DAMAGE AND IMPROVE LONG TERM DATA RETENTION
App. No. 14/565,729
→
MEMORY SYSTEM AND METHOD FOR SELECTING MEMORY DIES TO PERFORM MEMORY ACCESS OPERATIONS IN BASED ON MEMORY DIE TEMPERATURES
App. No. 14/565,125
→
THREE-DIMENSIONAL MEMORY STRUCTURE HAVING A BACK GATE ELECTRODE
App. No. 14/564,526
→
Re-Ordering NAND Flash Commands for Optimal Throughput and Providing a Specified Quality-of-Service
App. No. 14/565,241
→
Rewritable Multibit Non-Volatile Memory With Soft Decode Optimization
App. No. 14/563,820
→
DATA PROGRAMMING FOR A MEMORY HAVING A THREE-DIMENSIONAL MEMORY CONFIGURATION
App. No. 14/561,446
→
Storage Module, Host, and Method for Securing Data with Application Information
App. No. 14/560,670
→
SELECTIVE FLOATING GATE SEMICONDUCTOR MATERIAL DEPOSITION IN A THREE-DIMENSIONAL MEMORY STRUCTURE
App. No. 14/560,351
→
INTRINSIC MEMORY BLOCK HEALTH MONITORING
App. No. 14/560,698
→
UPDATING READ VOLTAGES USING SYNDROME WEIGHT COMPARISONS
App. No. 14/561,084
→
METHODS OF FABRICATING MEMORY DEVICE WITH SPACED-APART SEMICONDUCTOR CHARGE STORAGE REGIONS
App. No. 14/560,308
→