IP Library Patent Application 14584388
Patent Application
App. No. 14/584,388

Systems and Methods for Choosing a Memory Block for the Storage of Data Based on a Frequency With Which the Data is Updated

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Quick Facts
Patent No.
US None
App. No.
14/584,388
Abstract

Systems and methods for choosing a memory block for the storage of data based on a frequency with which data is updated are disclosed. In one implementation, a memory management module of a non-volatile memory system receives a request to open a free memory block for the storage of data. The memory management module determines a frequency with which the data is updated. The memory management module then opens a memory block of a first portion a free block list that is associated with low program/erase cycle counts in response to determining that the data will be frequently updated or opens a memory block of a second different portion of the free block list that is associated with high program/erase cycle counts in response to determining that the data is not frequently updated. The memory management module then stores the data in the open memory block of the non-volatile memory.

Claims (32)

1 . In a memory management module of a non-volatile memory system that is coupled with a host device, a method comprising:

receiving a request to open a free memory block of a non-volatile memory of the non-volatile memory system for the storage of data;

determining a frequency with which the data is updated;

opening a memory block of a first portion a free block list that is associated with low program/erase cycle counts in response to determining that the data will be frequently updated;

opening a memory block of a second different portion of the free block list that is associated with high program/erase cycle counts in response to determining that the data is not frequently updated; and

storing the data in the open memory block of the non-volatile memory.

2 . The method of claim 1 , wherein opening a memory block of a first portion a free block list that is associated with low program/erase cycle counts in response to determining that the data will be frequently updated comprises opening a memory block with a lowest program/erase cycle count on the free block list; and

wherein opening a memory block of a second different portion of the free block list that is associated with high program/erase cycle counts in response to determining that the data is not frequently updated comprises opening a memory block with a highest program/erase cycle count on the free block list.

3 . The method of claim 1 , wherein opening a memory block of a first portion a free block list that is associated with low program/erase cycle counts in response to determining that the data will be frequently updated comprises randomly selecting a memory block from the first portion of memory blocks to open; and

wherein opening a memory block of a second different portion of the free block list that is associated with high program/erase cycle counts in response to determining that the data is not frequently updated comprises randomly selecting a memory block from the second portion of memory blocks to open.

4 . The method of claim 1 , where a number of memory blocks in the first portion of the free block list is different than a number of memory blocks in the second portion of the free block list.

5 . The method of claim 1 , wherein the free block list comprises a circular array ranked in order of a program/erase cycle count associated with each memory block.

6 . The method of claim 1 , wherein the free block list comprises a linear array ranked in order of a program/erase cycle count associated with each memory block.

7 . The method of claim 1 , wherein the non-volatile memory comprises a silicon substrate and a plurality of memory cells forming at least two memory layers vertically disposed with respect to each other to form a monolithic three-dimensional structure, wherein at least one layer is vertically disposed with respect to the silicon substrate.

8 . An apparatus comprising:

non-volatile memory; and

processing circuitry in communication with the non-volatile memory, the processing circuitry comprising:

a memory management module configured to determine a frequency with which data is updated, select a memory block of the non-volatile memory to store the data based on an indication of how many further program/erase cycles that a block of memory can sustain and how frequently the data is updated, and open the selected memory block and store the data at the selected memory block of non-volatile memory.

9 . The apparatus of claim 8 , wherein the memory management module is configured to select the memory block to store the data from a free block list that is ranked in order of program/erase cycle counts associated with each memory block.

10 . The apparatus of claim 9 , where to select a memory block to store the data, the memory management module is configured to randomly select a memory block from a portion of the free block list that includes memory blocks associated with program/erase cycle counts that complement the frequency with which the data is updated.

11 . The apparatus of claim 9 , wherein the free block list is a circular array.

12 . The apparatus of claim 8 , wherein the non-volatile memory comprises a silicon substrate and a plurality of memory cells forming at least two memory layers vertically disposed with respect to each other to form a monolithic three-dimensional structure, wherein at least one layer is vertically disposed with respect to the silicon substrate.

13 . In a memory management module of a non-volatile memory system coupled to a host device, a method comprising:

classifying data based on a temperature of the data;

selecting a free memory block of a non-volatile memory of the memory system that complements the data based on a program/erase cycle count associated with the memory block and the temperature of the data; and

storing the data at the selected memory block.

14 . The method of claim 13 , wherein the memory block is selected from a portion of a free block list that includes free memory blocks associated with program/erase cycle counts that complement the temperature of the data.

15 . The method of claim 14 , wherein the memory block is randomly selected from the portion of the free block list.

16 . The method of claim 14 , wherein the free block list includes portions to complement at least two temperatures of data.

17 . The method of claim 13 , wherein selecting a memory block that complements the data comprises selecting a memory block associated with a high relative program/erase cycle count to complement cold data.

18 . The method of claim 13 , wherein selecting a memory block that complements the data comprises selecting a memory block associated with a low relative program/erase cycle count to complement hot data.

19 . The method of claim 13 , wherein the non-volatile memory comprises a silicon substrate and a plurality of memory cells forming at least two memory layers vertically disposed with respect to each other to form a monolithic three-dimensional structure, wherein at least one layer is vertically disposed with respect to the silicon substrate.

Assignments (2)
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038807/0807 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2014
From: PATEL, LEENA
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 034599/0217 →