Independent sense amplifier addressing and quota sharing in non-volatile memory
View Patent ↗Independent sense amplifier addressing provides separate column addresses to individual sense amplifier groups within a single bay during one column address cycle. A memory system determines whether the individual memory cells or bits of a column at a bay can be skipped. For each sense amplifier group having at least one memory cell (or bit) that needs to be programmed, the system determines for the first column address whether the memory cell can be skipped. If a bit or memory cell having a first column address from the sense amplifier group can be skipped, the system determines a next bit having a column address from the group that needs to be programmed. The system groups the next column address for programming during the first column address cycle. The system can program a different column address for different sense amplifier groups within the bay during a single column address cycle.
1. A non-volatile memory system, comprising:
a bay of non-volatile storage elements configured for programming in a plurality of column address cycles, wherein the bay includes a first group of non-volatile storage elements associated with a plurality of columns and a second group of non-volatile storage elements associated with the plurality of columns;
a first sense amplifier circuit associated with the first group of non-volatile storage elements of the bay, wherein the first sense amplifier circuit is configured to program in a first column address cycle a second non-volatile storage element of the first group having a second column address in response to determining that the second non-volatile storage element should be programmed and a first non-volatile storage element of the first group having a first column address can be skipped; and
a second sense amplifier circuit associated with the second group of non-volatile storage elements of the bay, wherein the second sense amplifier circuit is configured to program in the first column address cycle a first non-volatile storage element of the second group having the first column address in response to determining that the first non-volatile storage element of the second group should be programmed.
2. The non-volatile memory system of claim 1 , wherein:
the first sense amplifier circuit and the second sense amplifier circuit are configured to receive program data for the bay of non-volatile storage elements;
the first sense amplifier circuit includes a first priority encoder that is configured to generate from the program data the second column address in response to program data indicating that a first column can be skipped and a second column should be programmed; and
the second sense amplifier circuit includes a second priority encoder that is configured to generate from the program data the first column address in response to program data indicating that a first column should be programmed.
3. The non-volatile memory system of claim 2 , further comprising:
one or more control circuits in communication with the first sense amplifier circuit and the second sense amplifier circuit, the one or more control circuits are configured to read memory data from the bay of non-volatile storage elements prior to writing a set of user data and compare the set of user data to the memory data to determine whether programming can be skipped for each non-volatile storage element of the bay, the one or more control circuits are configured to generate the program data to indicate a subset of non-volatile storage elements to be programmed for the bay based on comparing the set of user data to the memory data.
4. The non-volatile memory system of claim 3 , wherein:
the one or more control circuits are configured to compare the set of user data to the memory data and determine that programming for the first non-volatile storage element of the first group can be skipped and that programming for the first non-volatile storage element of the second group should be performed, wherein the first non-volatile storage element of the first group and the first non-volatile storage element of the second group are part of the first column; and
the one or more control circuits are configured to compare the set of user data to the memory data and determine that programming for the second non-volatile storage element of the first group should be performed, wherein the second non-volatile storage element of the first group is part of the second column.
5. The non-volatile memory system of claim 1 , wherein:
the first group of non-volatile storage elements and the second group of non-volatile storage elements are part of a common word line in the bay of non-volatile storage elements; and
the bay of non-volatile storage elements is part of a monolithic three-dimensional non-volatile memory array.
6. A method of programming non-volatile storage, comprising:
programming a bay of non-volatile storage elements in a plurality of column address cycles, wherein the bay includes a first group of non-volatile storage elements associated with a plurality of columns and a second group of non-volatile storage elements associated with the plurality of columns;
programming by a first sense amplifier circuit in a first column address cycle a second non-volatile storage element of the first group having a second column address in response to determining that the second non-volatile storage element should be programmed and a first non-volatile storage element of the first group having a first column address can be skipped; and
programming by a second sense amplifier circuit in the first column address cycle a first non-volatile storage element of the second group having the first column address in response to determining that the first non-volatile storage element of the second group should be programmed.
7. The method of claim 6 , further comprising:
receiving by the first sense amplifier circuit and the second sense amplifier circuit program data for the bay of non-volatile storage elements;
generating from the program data by a first priority encoder of the first sense amplifier circuit the second column address in response to program data indicating that a first column can be skipped and a second column should be programmed; and
generating from the program data by a second priority encoder of the second sense amplifier circuit the first column address in response to program data indicating that a first column should be programmed.
8. The method of claim 7 , further comprising:
reading by one or more control circuits memory data from the bay of non-volatile storage elements prior to writing a set of user data;
comparing by the one or more control circuits the set of user data to the memory data to determine whether programming can be skipped for each non-volatile storage element of the bay; and
generating by the one or more control circuits the program data to indicate a subset of non-volatile storage elements to be programmed for the bay based on comparing the set of user data to the memory data.
9. The method of claim 8 , further comprising:
comparing by the one or more control circuits the set of user data to the memory data and determining that programming for the first non-volatile storage element of the first group can be skipped and that programming for the first non-volatile storage element of the second group should be performed, wherein the first non-volatile storage element of the first group and the first non-volatile storage element of the second group are part of the first column; and
comparing by the one or more control circuits the set of user data to the memory data and determining that programming for the second non-volatile storage element of the first group should be performed, wherein the second non-volatile storage element of the first group is part of the second column.
10. The method of claim 6 , wherein:
the first group of non-volatile storage elements and the second group of non-volatile storage elements are part of a common word line in the bay of non-volatile storage elements; and
the bay of non-volatile storage elements is part of a monolithic three-dimensional non-volatile memory array.