Initialization techniques for multi-level memory cells using multi-pass programming

1. A method for programming multi-level non-volatile memory cells, the multi-level non-volatile memory cells accessible by a plurality of word lines, the method comprising:

using a four-pass programming technique to program a block of the multi-level non-volatile memory cells;

detecting a power cycle before completing programming of the block of the multi-level non-volatile memory cells; and

upon power-up initialization, resuming programming on the block of the multi-level non-volatile memory cells by determining an error correction code read status associated with each word line in the block.

2. The method of claim 1 , wherein the multi-level non-volatile memory cells comprise three-bit memory cells.

3. The method of claim 1 , wherein each of the multi-level non-volatile memory cells stores a lower page data, a middle page data and an upper page data.

4. The method of claim 3 , wherein the four-pass programming technique comprises a first programming pass that is a function only of lower page data, and second through fourth programming passes that are a function of lower page data, middle page data and upper page data.

5. The method of claim 1 , wherein the four-pass programming technique comprises a first phase and a second phase, wherein the first phase comprises a non-sequential word line programming order, and the second phase comprises a sequential word line programming order.

6. The method of claim 1 , wherein resuming programming on the block of the multi-level non-volatile memory cells comprises resuming programming based on predetermined error correction code read status patterns in the block.

7. The method of claim 1 , wherein resuming programming on the block of the multi-level non-volatile memory cells comprises determining if (a) some of the multi-level non-volatile memory cells in the block are in an erase state, (b) all of the multi-level non-volatile memory cells in the block are in an invalid data state, and (c) some of the multi-level non-volatile memory cells in the block are in a valid data state.

8. The method of claim 7 , wherein:

if some of the multi-level non-volatile memory cells in the block are in an erase state, resuming programming on the block of the multi-level non-volatile memory cells comprises:

determining a word line having non-volatile memory cells in the block in an erase state adjacent a word line having non-volatile memory cells in the block in a data invalid state; and

resuming programming on the determined word line with a first programming pass;

if all of the multi-level non-volatile memory cells in the block are in an invalid data state, resuming programming on the block of the multi-level non-volatile memory cells comprises:

resuming programming on a first word line in the current block with a fourth programming pass ; and

if some of the multi-level non-volatile memory cells in the block are in a valid data state, resuming programming on the block of the multi-level non-volatile memory cells comprises:

determining a word line having non-volatile memory cells in the block in a data invalid state adjacent a word line having non-volatile memory cells in the block in a data valid state; and

resuming programming on the determined word line with the fourth programming pass.

9. A non-volatile memory comprising:

an array of multi-level memory cells organized into blocks wherein memory cells of each block are erasable together and are accessible by a plurality of word lines; and

a controller for operating a program operation comprising:

using a four-pass programming technique to program a block of the multi-level memory cells;

detecting a power cycle before completing programming of the block of the multi-level memory cells; and

upon power-up initialization, resuming programming on the block of the multi-level memory cells by determining an error correction code read status associated with each word line in the block.

10. The non-volatile memory of claim 9 , wherein the multi-level memory cells comprise three-bit memory cells.

11. The non-volatile memory of claim 9 , wherein each of the multi-level memory cells stores a lower page data, a middle page data and an upper page data.

12. The non-volatile memory of claim 11 , wherein the four-pass programming technique comprises a first programming pass that is a function only of lower page data, and second through fourth programming passes that are a function of lower page data, middle page data and upper page data.

13. The non-volatile memory of claim 9 , wherein the four-pass programming technique comprises a first phase and a second phase, wherein the first phase comprises a non-sequential word line programming order, and the second phase comprises a sequential word line programming order.

14. The non-volatile memory of claim 9 , wherein resuming programming on the block of the multi-level non-volatile memory cells comprises resuming programming based on predetermined error correction code read status patterns in the block.

15. The non-volatile memory of claim 9 , wherein resuming programming on the block of the multi-level non-volatile memory cells comprises determining if (a) some of the multi-level non-volatile memory cells in the block are in an erase state, (b) all of the multi-level non-volatile memory cells in the block are in an invalid data state, and (c) some of the multi-level non-volatile memory cells in the block are in a valid data state.

16. The non-volatile memory of claim 15 , wherein:

if some of the multi-level non-volatile memory cells in the block are in an erase state, resuming programming on the block of the multi-level non-volatile memory cells comprises:

determining a word line having non-volatile memory cells in the block in an erase state adjacent a word line having non-volatile memory cells in the block in a data invalid state; and

resuming programming on the determined word line with a first programming pass;

if all of the multi-level non-volatile memory cells in the block are in an invalid data state, resuming programming on the block of the multi-level non-volatile memory cells comprises:

resuming programming on a first word line in the current block with a fourth programming pass ; and

if some of the multi-level non-volatile memory cells in the block are in a valid data state, resuming programming on the block of the multi-level non-volatile memory cells comprises:

determining a word line having non-volatile memory cells in the block in a data invalid state adjacent a word line having non-volatile memory cells in the block in a data valid state; and

resuming programming on the determined word line with the fourth programming pass.

17. A method for use with three-bit non-volatile memory cells, the three-bit non-volatile memory cells accessible by a plurality of word lines, the method comprising:

detecting a power cycle before completing a four-pass programming of a block of the three-bit non-volatile memory cells; and

upon power-up initialization, resuming four-pass programming on the block of the three-bit non-volatile memory cells by:

determining if (a) some of the three-bit non-volatile memory cells in the block are in an erase state, (b) all of the three-bit non-volatile memory cells in the block are in an invalid data state, and (c) some of the three-bit non-volatile memory cells in the block are in a valid data state.

18. The method of claim 17 , wherein:

each of the three-bit non-volatile memory cells stores a lower page data, a middle page data and an upper page data; and

four-pass programming comprises a first programming pass that is a function only of lower page data, and second through fourth programming passes that are a function of lower page data, middle page data and upper page data.

19. The method of claim 17 , wherein four-pass programming technique comprises a first phase and a second phase, wherein the first phase comprises a non-sequential word line programming order, and the second phase comprises a sequential word line programming order.

20. The method of claim 17 , wherein:

if some of the three-bit non-volatile memory cells in the block are in an erase state, resuming four-pass programming on the block of the multi-level non-volatile memory cells comprises:

determining a word line having non-volatile memory cells in the block in an erase state adjacent a word line having non-volatile memory cells in the block in a data invalid state; and

resuming four-pass programming on the determined word line with a first programming pass;

if all of the three-bit non-volatile memory cells in the block are in an invalid data state, resuming four-pass programming on the block of the multi-level non-volatile memory cells:

resuming four-pass programming on a first word line in the current block with a fourth programming pass ; and

if some of the three-bit non-volatile memory cells in the block are in a valid data state, resuming four-pass programming on the block of the multi-level non-volatile memory cells:

determining a word line having non-volatile memory cells in the block in a data invalid state adjacent a word line having non-volatile memory cells in the block in a data valid state; and

resuming four-pass programming on the determined word line with the fourth programming pass.