Multi-clock generation through phase locked loop (PLL) reference
A circuit for providing a plurality of clock signals of differing frequencies includes: a phase locked loop section including a first voltage controller oscillator, connected to receive a reference clock value and generate therefrom a first voltage level, wherein the first voltage controller oscillator receives the first voltage level and generates therefrom a first clock signal; and one or more second voltage controller oscillators, each connected to receive the first voltage level, a corresponding trim value and a corresponding control voltage and derive therefrom a corresponding second clock signal.
1. A circuit for providing a plurality of clock signals of differing frequencies, comprising:
a phase locked loop section connected to receive a reference clock value and provide a first clock signal, including a first voltage controlled oscillator connected to receive a first voltage level and generate therefrom the first clock signal, the first voltage level being generated by the phase locked loop section based upon the reference clock value and feedback from the first clock signal; and
one or more second voltage controller oscillators, each connected to receive the first voltage level and a corresponding trim value and, concurrently with the generating of the first clock signal, generate therefrom a respective second clock signal having a frequency dependent upon the first voltage level and corresponding trim value,
wherein one or more of the second voltage controlled oscillators is further connected to receive a corresponding control voltage, the respective second clock signal having a frequency further dependent upon the corresponding control voltage's level, and
wherein the one or more second voltage controlled oscillators increase the frequency of the respective second clock signal in response to the corresponding control voltage's level increasing.
2. The circuit of claim 1 , wherein the one or more second voltage controlled oscillators connected to receive the corresponding control voltage are connected to provide the respective second clock signals to one or more corresponding charge pump circuits for use in the regulation thereof, the corresponding control voltage's level being derived from the corresponding charge pump's output level.
3. The circuit of claim 1 , wherein each of the one or more second voltage controlled oscillators includes a corresponding first transistor connected to increase a current flowing through the corresponding second voltage controlled oscillator in response to the corresponding control voltage's level.
4. The circuit of claim 1 , wherein the phase locked loop section further includes:
a phase/frequency detector connected to receive the reference clock value and the feedback from the first clock signal and generate therefrom up/down control values; and
a charge pump connected to receive the up/down control values and generate therefrom the first voltage level.
5. The circuit of claim 4 , wherein the phase locked loop further comprises:
a low pass filter through which the first voltage level is provided to the first voltage controller oscillator.
6. The circuit of claim 4 , wherein the phase locked loop further comprises:
a frequency divider connected to receive the first clock signal and generate therefrom the feedback from the first clock signal.
7. The circuit of claim 1 , wherein the circuit is formed on an integrated circuit further comprising:
a reference clock generation circuit to generate the reference clock value.
8. The circuit of claim 1 , wherein the circuit is formed on a monolithic two-dimensional semiconductor memory device having memory cells arranged in a single physical level above a silicon substrate and comprise a charge storage medium.
9. The circuit of claim 1 , wherein the circuit is formed on a monolithic three-dimensional semiconductor memory device having memory cells arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.
10. A circuit for providing a plurality of clock signals of differing frequencies, comprising:
a phase locked loop section connected to receive a reference clock value and provide a first clock signal, including a first voltage controlled oscillator connected to receive a first voltage level and generate therefrom the first clock signal, the first voltage level being generated by the phase locked loop section based upon the reference clock value and feedback from the first clock signal; and
one or more second voltage controller oscillators, each connected to receive the first voltage level and a corresponding trim value and, concurrently with the generating of the first clock signal, generate therefrom a respective second clock signal having a frequency dependent upon the first voltage level and corresponding trim value,
wherein one or more of the second voltage controlled oscillators is further connected to receive a corresponding control voltage, the respective second clock signal having a frequency further dependent upon the corresponding control voltage's level, and
wherein the one or more second voltage controlled oscillators decrease the frequency of the respective second clock signal in response to the corresponding control voltage's level increasing.
11. The circuit of claim 10 , wherein each of the one or more second voltage controlled oscillators includes a corresponding first transistor connected to decrease a current flowing through the corresponding second voltage controlled oscillator in response to the corresponding control voltage's level.
12. The circuit of claim 10 , wherein the one or more second voltage controlled oscillators connected to receive the corresponding control voltage are connected to provide the respective second clock signals to one or more corresponding charge pump circuits for use in the regulation thereof, the corresponding control voltage's level being derived from the corresponding charge pump's output level.
13. The circuit of claim 10 , wherein the phase locked loop section further includes:
a phase/frequency detector connected to receive the reference clock value and the feedback from the first clock signal and generate therefrom up/down control values; and
a charge pump connected to receive the up/down control values and generate therefrom the first voltage level.
14. The circuit of claim 13 , wherein the phase locked loop further comprises:
a low pass filter through which the first voltage level is provided to the first voltage controller oscillator.
15. The circuit of claim 13 , wherein the phase locked loop further comprises:
a frequency divider connected to receive the first clock signal and generate therefrom the feedback from the first clock signal.
16. The circuit of claim 10 , wherein the circuit is formed on an integrated circuit further comprising:
a reference clock generation circuit to generate the reference clock value.
17. The circuit of claim 10 , wherein the circuit is formed on a monolithic two-dimensional semiconductor memory device having memory cells arranged in a single physical level above a silicon substrate and comprise a charge storage medium.
18. The circuit of claim 10 , wherein the circuit is formed on a monolithic three-dimensional semiconductor memory device having memory cells arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.