Patent Assignment
Reel/Frame 069796/0423
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2024-12-31
Received: 2024-12-31
Pages: 266
Assignor
SANDISK TECHNOLOGIES LLC
Executed: 2024-12-27
Assignee
SANDISK TECHNOLOGIES, INC.
951 SANDISK DRIVE, LEGAL DEP., MILPITAS, CA, 95035, UNITED STATES
Covered Applications
(100)
THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/887,781
→
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SILICON OXYCARBIDE LINERS AND METHODS OF FORMING THE SAME
App. No. 18/830,035
→
COUNTERMEASURE FOR DRAIN-SIDE SELECT GATE UPPER TAIL
App. No. 18/825,599
→
THREE-DIMENSIONAL MEMORY DEVICE WITH LATERALLY INTEGRATED ACCESS TRANSISTORS AND METHOD OF MAKING THE SAME
App. No. 18/819,475
→
THREE-DIMENSIONAL MEMORY DEVICE WITH LATERALLY INTEGRATED ACCESS TRANSISTORS AND METHOD OF MAKING THE SAME
App. No. 18/819,569
→
OPTICAL INSPECTION TOOL INCLUDING FIELD APERTURE SYSTEM HAVING DIFFERENT TRANSMITTANCE FOR DIFFERENT RADIATION WAVELENGTHS AND METHOD OF USING THEREOF
App. No. 18/816,706
→
DIODE CONTAINING BIT LINE BIAS STRUCTURE AND METHODS FOR FORMING THE SAME
App. No. 18/811,152
→
THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/805,051
→
THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/805,193
→
THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME
App. No. 18/800,545
→
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MULTI-LEVEL BRIDGE SUPPORT STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/798,250
→
THREE-DIMENSIONAL MEMORY DEVICE WITH TUBULAR CHANNELS AND INTEGRATED ACCESS TRANSISTORS AND METHOD OF MAKING THE SAME
App. No. 18/794,873
→
MEMORY DEVICE INCLUDING A GERMANIUM-CONTAINING SOURCE STRUCTURE AND METHODS FOR FORMING THE SAME
App. No. 18/794,727
→
THREE-DIMENSIONAL MEMORY DEVICE WITH LATERALLY INTEGRATED ACCESS TRANSISTORS AND METHOD OF MAKING THE SAME
App. No. 18/794,809
→
THREE-DIMENSIONAL MEMORY DEVICE WITH BIT LINES LOCATED IN DIFFERENT VERTICAL LEVELS AND METHOD OF MAKING THE SAME
App. No. 18/791,823
→
MAGNETORESISTIVE MEMORY DEVICES INCLUDING DUAL FREE LAYERS AND METHODS FOR MAKING AND OPERATING THE SAME
App. No. 18/790,599
→
MAGNETORESISTIVE MEMORY DEVICES INCLUDING DUAL FREE LAYERS AND METHODS FOR MAKING AND OPERATING THE SAME
App. No. 18/790,557
→
MULTILAYER TRENCH CAPACITOR AND METHOD OF MAKING THE SAME
App. No. 18/788,942
→
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ETCH STOP METAL PLATES FOR BACKSIDE VIA STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/788,855
→
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING TOP SOURCE CONTACT TO DOPED SEMICONDUCTOR SOURCE TIPS AND METHODS FOR FORMING THE SAME
App. No. 18/789,145
→
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING TOP SOURCE CONTACT TO DOPED SEMICONDUCTOR SOURCE TIPS AND METHODS FOR FORMING THE SAME
App. No. 18/789,041
→
MEMORY DEVICE INCLUDING A CORE-SIDE CHARGE TRAPPING MATERIAL LAYER AND METHODS FOR FORMING THE SAME
App. No. 18/787,367
→
THREE-DIMENSIONAL MEMORY DEVICE WITH SLANTED STEPS IN A STAIRCASE REGION AND METHOD OF FORMING THE SAME
App. No. 18/787,247
→
THREE-DIMENSIONAL MEMORY DEVICE HAVING A COMPACT WORD LINE DRIVER TRANSISTOR LAYOUT
App. No. 18/785,932
→
THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT ASSEMBLIES AND METHODS FOR FORMING THE SAME
App. No. 18/784,263
→
THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT ASSEMBLIES AND METHODS FOR FORMING THE SAME
App. No. 18/784,146
→
VOLTAGE-CONTROLLED MAGNETIC ANISOTROPY DEVICE INCLUDING AN ON-CHIP ELECTROMAGNET
App. No. 18/784,034
→
THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT ASSEMBLIES AND METHODS FOR FORMING THE SAME
App. No. 18/784,218
→
STT MRAM DEVICE WITH PERPENDICULAR EXCHANGE BIAS LAYER IN CONTACT WITH FREE LAYER
App. No. 18/781,035
→
CAPACITOR WITH AN INTRA-ELECTRODE OXYGEN CONTAINING INTERFACIAL LAYER AND METHOD OF MAKING THE SAME
App. No. 18/779,616
→
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING COAXIAL DOUBLE CONTACT VIA STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/779,508
→
HIGHEST DATA STATE PROGRAM-VERIFY SKIP FOR PROGRAM PERFORMANCE IMPROVEMENT
App. No. 18/776,354
→
HOLE PRE-CHARGE FROM BITLINE SIDE TO ENABLE FULL REVERSE ORDER PROGRAM SUB-BLOCK MODE
App. No. 18/776,359
→
DUAL WORD LINE ALL-STRING PREPROGRAM FOR LATERAL DATA RETENTION IMPROVEMENT
App. No. 18/776,363
→
TUNNELING BARRIER RESISTOR AND METHODS FOR FORMING THE SAME
App. No. 18/774,112
→
THREE-DIMENSIONAL MEMORY CONTAINING ETCH-STOP ISOLATION CAPS OVER LATERAL ISOLATION STRUCTURES AND METHOD OF MAKING THE SAME
App. No. 18/771,091
→
SEMICONDUCTOR DEVICE INCLUDING LASER BEAM ABSORPTION ENHANCEMENT STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/768,833
→
SEMICONDUCTOR DEVICE INCLUDING LASER BEAM ABSORPTION ENHANCEMENT STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/768,888
→
THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/763,704
→
NON-VOLATILE MEMORY WITH EARLY TERMINATION FOR THRESHOLD VOLTAGE TRACKING
App. No. 18/763,435
→
SUSPEND-RESUME-GO TECHNIQUES FOR MEMORY DEVICES
App. No. 18/757,857
→
XOR DATA RECOVERY SCHEMES NONVOLATILE MEMORY DEVICES
App. No. 18/754,911
→
IN-PLACE REFRESH TECHNIQUES FOR NON-VOLATILE MEMORY DEVICES
App. No. 18/754,901
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AUTHENTICATING A HOST COMPUTER SYSTEM TO ACCESS A DATA STORAGE DEVICE
App. No. 18/753,968
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DATA RECOVERY IN NONVOLATILE MEMORY WITH DEFECTIVE WORD LINE
App. No. 18/749,669
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SEMICONDUCTOR DEVICE INCLUDING AN INTEGRATED TIM-ON-DIE
App. No. 18/748,383
→
PROGRAMMING WITHOUT PRE-CHARGE IN NONVOLATILE MEMORY DEVICES
App. No. 18/748,836
→
STEP VOLTAGE DURING CURRENT FORCE READ OF PROGRAMMABLE RESISTANCE MEMORY CELL WITH THRESHOLD SWITCHING SELECTOR
App. No. 18/749,289
→
CAPACITOR FOR SNAPBACK CURRENT MITIGATION
App. No. 18/749,383
→
ARTIFICIAL INTELLIGENCE TRAINING SYSTEM
App. No. 18/748,826
→
CIRCUIT SNAPBACK AND CHARGE DIVERSION FOR CROSS-POINT ARRAYS
App. No. 18/747,626
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PROGRAM TIME IMPROVEMENT FOR NAND DIE WITH COARSE BITSCAN DURING PROGRAM-VERIFY
App. No. 18/747,805
→
MEMORY WITH WRITE ADDRESS DELAY CIRCUIT
App. No. 18/747,497
→
STORAGE DEVICE HEAT-MITIGATING ENCLOSURE
App. No. 18/747,860
→
COMPARATOR FOR HIGH SPEED INTERFACE
App. No. 18/747,500
→
HARDWARE WALLET AND METHOD TO SECURELY SIGN A TRANSACTION WITH A HARDWARE WALLET
App. No. 18/747,354
→
METHOD AND DEVICE FOR SECURING USER DATA ON A DATA STORAGE DEVICE
App. No. 18/747,422
→
METHOD TO PREVENT DATA THEFT FROM A STORAGE DEVICE
App. No. 18/743,113
→
PROACTIVE ERROR DETECTION IN A MEMORY DEVICE
App. No. 18/743,421
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SEMICONDUCTOR DEVICE INCLUDING AN INTEGRATED WAFER LEVEL HEAT SINK WINDOW PLATE
App. No. 18/740,674
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STATE DEPENDENT VERIFY VOLTAGE RAMPING TIME PERIODS FOR A PROGRAM-VERIFY OPERATION FOR PERFORMANCE GAIN
App. No. 18/740,793
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CONVERTING A SOLID-STATE DRIVE OPERATING IN A FIRST MODE TO ANOTHER SOLID-STATE DRIVE OPERATING IN A SECOND MODE
App. No. 18/740,086
→
ELECTRONIC DEVICE HAVING A DOUBLE-WALLED HOUSING THAT ACTS AS A THERMAL BARRIER
App. No. 18/739,566
→
HIGH BANDWIDTH NON-VOLATILE MEMORY
App. No. 18/739,168
→
REDUCING INTERFERENCE METHODS FOR 3D MULTIPLE-CHANNEL MEMORY DEVICES
App. No. 18/737,813
→
Data Storage Device and Method for Defining Caching Layers Based on Cache Attributes
App. No. 18/736,948
→
Data Storage Device and Method for Writing Updates to a Host Memory Buffer Using Assistance from a Host
App. No. 18/736,977
→
PARTIAL PAGE IN-PLACE REFRESH
App. No. 18/737,678
→
DYNAMIC NAND STATUS TIMING ADJUSTMENTS WITH CLOSED LOOP FEEDBACK
App. No. 18/736,656
→
SEMICONDUCTOR DEVICE INCLUDING A THERMAL RELIEF LAYER
App. No. 18/737,427
→
IN-PLACE READ REFRESH TECHNIQUES FOR NONVOLATILE MEMORY DEVICES
App. No. 18/737,819
→
VARIABLE FAST LOOK NEIGHBOR AHEAD TO IMPROVE READ ACCURACY
App. No. 18/735,803
→
Data Storage Device and Method for Bypassing a Read-Only Mode to Allow User Data Backup
App. No. 18/735,878
→
QUICK PASS WRITE WITH QUASI-LOW VERIFY HIGH LEVEL
App. No. 18/735,812
→
Data Storage Device and Method for Classifying a Set of Continuous Wordlines as an Outlier Band in an Open Block
App. No. 18/735,710
→
DATA STORAGE DEVICE AND METHOD OF ACCESS WITH USER FINGERPRINT
App. No. 18/735,182
→
SEMICONDUCTOR PACKAGE HAVING A SEMICONDUCTOR DIE LAYER
App. No. 18/735,529
→
SUPPORTING MIXED READ IN NON-VOLATILE MEMORY CONTROLLER
App. No. 18/734,666
→
Data Storage Device and Method for Video Processing and Video Frame Searching Using a Key-Value
App. No. 18/734,516
→
SLC SUB-BLOCK MODE FOR NONVOLATILE MEMORY DEVICES
App. No. 18/734,019
→
READ REFRESH TECHNIQUES FOR NONVOLATILE MEMORY DEVICES
App. No. 18/733,996
→
Data Storage Device and Method for Storing Selected Data in Relatively-Lower Data Retention Pages of a Quad-Level Cell Memory
App. No. 18/733,238
→
UNMATCHED DATA PATH DELAY COMPENSATION FOR NON-VOLATILE MEMORY
App. No. 18/732,423
→
APPARATUS AND METHODS FOR NEGATIVE THRESHOLD VOLTAGES FOR NONVOLATILE MEMORY DEVICES
App. No. 18/731,253
→
READ/WRITE CIRCUITS FOR MULTI-STORY CROSS-POINT MEMORY
App. No. 18/679,474
→
FAKE FAST PLANE DETECTION IN EARLY PROGRAM TERMINATION
App. No. 18/680,066
→
DISCHARGE-FREE READ OPERATIONS FOR HIGH BANDWIDTH NONVOLATILE MEMORY DEVICES
App. No. 18/678,647
→
IMPLEMENTATION OF HIERARCHICAL NAVIGABLE SMALL WORLD (HNSW) SEARCH TECHNIQUES USING NAND MEMORY
App. No. 18/678,692
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MEMORY DEVICE WITH ALTERNATE BIT LINE SENSING
App. No. 18/679,415
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Data Storage Device and Method for Garbage Collection in a Multi-Tier Memory
App. No. 18/676,929
→
Data Storage Device and Method for Thermal Management Through Command Selection
App. No. 18/676,911
→
SUSPEND-RESUME-GO TECHNIQUES FOR MEMORY DEVICES
App. No. 18/677,632
→
Video Data Management Based on Data Storage Device Terabytes Written
App. No. 18/677,111
→
Data Storage Device and Method for Transaction Recovery Using Extra Timeout
App. No. 18/676,886
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MEMORY DEVICE INCLUDING SELF-ALIGNED DIELECTRIC BASE BELOW WORD LINE CONTACT VIA STRUCTURE AND METHOD FOR FORMING THE SAME
App. No. 18/675,721
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NON-VOLATILE MEMORY WITH LOCATION DEPENDENT BITLINE VOLTAGE DURING PROGRAM-VERIFY FOR CURRENT SENSING COMPENSATION
App. No. 18/676,146
→
APPARATUS AND METHODS FOR HOLE CURRENT PROGRAM VERIFY OPERATIONS
App. No. 18/675,685
→
APPARATUS AND METHODS FOR DECODER MODULE ARCHITECTURES FOR NON-VOLATILE MEMORY
App. No. 18/676,166
→
BACKGROUND DUTY CYCLE CORRECTION IN UNSELECTED DIE
App. No. 18/673,786
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GENERATION OF A DEEPER NEGATIVE VOLTAGE USING CHARGE-PUMP TO REDUCE CHIP AREA AND CURRENT CONSUMPTION
App. No. 18/674,765
→