Step voltage during current force read of programmable resistance memory cell with threshold switching selector
Technology for reading memory cells in a cross-point memory array. Each memory cell has a threshold switching selector in series with a programmable resistance memory element. The memory system applies a step voltage pulse during a current force read of programmable resistance memory cells in a cross-bar memory array. In an aspect, the step voltage pulse is used to switch on the threshold switching selector. In an aspect, the step voltage pulse is applied after the threshold switching selector switches on when a snapback current may be present. In an aspect, the step voltage pulse is applied after the snapback current has dissipated.
1 . An apparatus comprising:
one or more control circuits configured to communicate with a cross-point memory structure having first conductive lines, second conductive lines, and memory cells, each memory cell at a crosspoint of a first conductive line and a second conductive line, each memory cell having a programmable resistance memory element in series with a threshold switching selector;
the one or more control circuits configured to:
apply a fixed magnitude read current to a selected first conductive line while a selected second conductive line is at a select voltage, the selected first conductive line connected to a selected memory cell;
apply a step voltage to the selected first conductive line while the threshold switching selector is on; and
sense the selected memory cell after the step voltage is removed from the selected first conductive line and while the fixed magnitude read current is driven through the selected memory cell.
2 . The apparatus of claim 1 , wherein the one or more control circuits are configured to:
begin to apply the step voltage to the selected first conductive line prior to the threshold switching selector turning on; and
continue to apply the step voltage to the selected first conductive line after the threshold switching selector has turned on.
3 . The apparatus of claim 1 , wherein the one or more control circuits are configured to:
begin to apply the step voltage to the selected first conductive line after the threshold switching selector of the selected memory cell turns on as a result of applying the fixed magnitude read current to the selected first conductive line.
4 . The apparatus of claim 3 , wherein the one or more control circuits are further configured to:
apply the step voltage to the selected first conductive line while a snapback current is present, the snapback current due to a voltage drop across the threshold switching selector after the threshold switching selector switches on.
5 . The apparatus of claim 3 , wherein the one or more control circuits are configured to:
begin to apply the step voltage to the selected first conductive line after a snapback current has dissipated, the snapback current due to a voltage drop across the threshold switching selector after the threshold switching selector switches on.
6 . The apparatus of claim 1 , wherein the one or more control circuits are configured to:
apply the step voltage to the selected first conductive line while a snapback current is present, the snapback current due to a voltage drop across the threshold switching selector after the threshold switching selector switches on.
7 . The apparatus of claim 1 , wherein the one or more control circuits are further configured to:
begin to apply the step voltage to the selected first conductive line after a snapback current has dissipated, the snapback current due to a voltage drop across the threshold switching selector after the threshold switching selector switches on.
8 . The apparatus of claim 1 , wherein the programmable resistance memory element comprises an MRAM element.
9 . The apparatus of claim 1 , wherein the threshold switching selector comprises an Ovonic Threshold Switch (OTS).
10 . The apparatus of claim 1 , wherein the step voltage comprises a step up voltage pulse.
11 . The apparatus of claim 1 , wherein the step voltage comprises a step down voltage pulse.
12 . The apparatus of claim 1 , wherein the step voltage comprises a power supply voltage.
13 . A method for reading a programmable resistance memory cell in a cross-point memory array, the method comprising:
applying a fixed magnitude read current to a selected first conductive line in the cross-point memory array while a selected second conductive line is at a select voltage, the fixed magnitude read current creates a voltage across a selected memory cell between the selected first conductive line and the selected second conductive line that turns on a threshold switching selector of the selected memory cell;
applying a step voltage pulse to the selected first conductive line after the threshold switching selector turns on and a snapback current is present; and
sensing the selected memory cell while the threshold switching selector is on and the fixed magnitude read current is driven through the selected memory cell.
14 . The method of claim 13 , wherein applying the step voltage pulse to the selected first conductive line comprises applying a step up voltage pulse to the selected first conductive line in response to a voltage across the selected memory cell falling.
15 . The method of claim 13 , wherein applying the step voltage pulse to the selected first conductive line comprises applying a step down voltage pulse to the selected first conductive line in response to a voltage across the selected memory cell falling.
16 . A memory system, comprising:
a cross-point memory structure having first conductive lines, second conductive lines, and memory cells, each memory cell at a crosspoint of a first conductive line and a second conductive line, each memory cell having a programmable resistance memory element in series with a threshold switching selector; and
one or more control circuits in communication with the cross-point memory structure, the one or more control circuits configured to:
apply a fixed magnitude read current to a selected first conductive line while a selected second conductive line is at a select voltage, the fixed magnitude read current creates a voltage across a selected memory cell that turns on the threshold switching selector of the selected memory cell;
apply a step voltage pulse to the selected first conductive line after the threshold switching selector turns on; and
sense the selected memory cell after the step voltage pulse is removed from the selected first conductive line and while the fixed magnitude read current is driven through the selected memory cell.
17 . The memory system of claim 16 , wherein the one or more control circuits are configured to:
apply the step voltage pulse to the selected first conductive line while a snapback current is present, the snapback current due to a voltage drop across the threshold switching selector after the threshold switching selector switches on.
18 . The memory system of claim 16 , wherein the one or more control circuits are configured to:
apply the step voltage pulse to the selected first conductive line after a snapback current has dissipated, the snapback current due to a voltage drop across the threshold switching selector after the threshold switching selector switches on.
19 . The memory system of claim 16 , wherein:
the select voltage applied to the second selected conductive line is ground; and
the one or more control circuits are configured to apply the step voltage pulse to the selected first conductive line as a step-up voltage pulse.
20 . The memory system of claim 16 , wherein:
the select voltage applied to the second selected conductive line is a high voltage; and
the one or more control circuits are configured to apply the step voltage pulse to the selected first conductive line as a step-down voltage pulse.