IP Library › Assignment 071382/0001
Patent Assignment
Reel/Frame 071382/0001

PARTIAL RELEASE OF SECURITY INTERESTS

Recorded: 2025-04-25 Received: 2025-04-25 Pages: 489
Assignor
Assignee
SANDISK TECHNOLOGIES, INC.
951 SANDISK DRIVE, MILPITAS, CA, 95035, UNITED STATES
Covered Applications (100)
Data Storage Device and Method for Bit Error Rate (BER) Balancing Based on Dynamic Sense Time
App. No. 19/035,315
→
Data Storage Device and Method for Non-Balanced Mapping for Variable Read Resolution
App. No. 19/035,262
→
PROTECTING DATA IN AN UNLOCKED STORAGE DEVICE
App. No. 19/033,889
→
HIGH-SPEED READ DATA CAPTURE IN FLASH MEMORY CONTROLLER
App. No. 19/032,518
→
OPTIMIZING SEARCHING OF LOGICAL-TO-PHYSICAL (L2P) ADDRESS TRANSLATION TABLE ENTRIES IN DATA STORAGE DEVICES
App. No. 19/032,509
→
Physical Encryption Techniques For Memory Devices
App. No. 19/032,927
→
DETECTING MICROCRACKS IN A SEMICONDUCTOR DIE
App. No. 19/029,740
→
MANAGEMENT OF DATA STORAGE DEVICE POWER CONSUMPTION
App. No. 19/022,787
→
SYSTEMS AND METHODS FOR STACKED MEMORY PACKAGING
App. No. 19/015,724
→
MEMORY DIE STATE TRANSITION TRACKING MECHANISM
App. No. 19/015,515
→
MITIGATION FOR CAPACITIVE COUPLING IN ELECTRICAL PATHWAYS IN NON-VOLATILE MEMORY DIES
App. No. 19/014,638
→
SEMICONDUCTOR DEVICES WITH PROTECTIVE LAYERS THAT FACILITATE DETECTION OF MICROCRACKS
App. No. 19/014,102
→
WIRELESS CHARGING-ENABLED DATA STORAGE DEVICE
App. No. 19/013,657
→
EARLY PROGRAM TERMINATION FOR NAND SLC PROGRAM
App. No. 19/012,158
→
THREE-DIMENSIONAL MEMORY DEVICE WITH STACKED STAIRCASE REGIONS AND METHODS FOR FORMING THE SAME
App. No. 19/010,801
→
HOST MANUAL REFRESH OPTIMIZATION FOR A DATA STORAGE DEVICE
App. No. 19/011,480
→
HIGH-PERFORMANCE MULTI-TIER SUB-BLOCK MODE IN A MEMORY DEVICE
App. No. 19/009,325
→
METHOD FOR PARALLEL HARDWARE INSTANCE CONFIGURATION
App. No. 19/009,238
→
Data Storage Device and Method for Enabling Orthogonal Parity
App. No. 19/009,125
→
NON-DESTRUCTIVE LOGICAL BLOCK ADDRESS SIZE CHANGE WITH A FORMAT COMMAND
App. No. 19/009,274
→
Translation And Data Management In Storage Devices
App. No. 19/008,107
→
Data Storage Device Holder
App. No. 29/981,741
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DIE AND PLANE LEVEL FAILURE RECOVERY SCHEME
App. No. 19/005,223
→
SEMICONDUCTOR DEVICE INCLUDING NARROW GAP UNDERFILL MATERIAL
App. No. 19/005,691
→
Power Consumption Fairness In Multi-Host System
App. No. 19/003,904
→
NON-VOLATILE MEMORY WITH SMART TAIL DETECTION READ MODE WITHOUT ERASE TIME PENALTY
App. No. 19/003,033
→
NON-VOLATILE MEMORY WITH DYNAMIC ERASE VOLTAGE
App. No. 19/000,937
→
MEMORY DEVICE INCLUDING A CORE-SIDE CHARGE TRAPPING MATERIAL LAYER AND METHODS FOR FORMING THE SAME
App. No. 18/989,549
→
MANAGING POWER STATES IN A DATA STORAGE DEVICE
App. No. 18/989,198
→
PRINTED CIRCUIT BOARD WITH HEALABLE FEATURES
App. No. 18/990,220
→
THERMAL SHUTDOWN HANDLING IN DATA STORAGE DEVICE
App. No. 18/989,133
→
SEMICONDUCTOR DEVICE INCLUDING AN ULTRATHIN CONTROLLER DIE
App. No. 18/988,097
→
FAILURE DETECTION AND REPAIR CIRCUITS FOR STACKED MEMORY ASSEMBLY
App. No. 18/985,101
→
APPARATUS AND METHODS FOR VERTICALLY STACKED INTEGRATED MEMORY ASSEMBLIES
App. No. 18/986,374
→
COMBINATION SINGLE-LEVEL CELL PROGRAM MODES TO IMPROVE CELL ENDURANCE
App. No. 18/986,018
→
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING SYMMETRIC ARRAY CONNECTION STRIPS AND METHODS FOR FORMING THE SAME
App. No. 18/984,145
→
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING SYMMETRIC ARRAY CONNECTION STRIPS AND METHODS FOR FORMING THE SAME
App. No. 18/984,190
→
SEMICONDUCTOR DEVICE INCLUDING VERTICAL WIRE BONDS
App. No. 18/982,848
→
CONFIGURABLE INPUT/OUTPUT DRIVER CIRCUITRY FOR CONTROLLER AND NAND COMMUNICATION IN A DATA STORAGE DEVICE
App. No. 18/983,213
→
EDGE WORD LINE BIAS ENGINEERING FOR THRESHOLD VOLTAGE MARGIN IMPROVEMENT OF SUB-BLOCK MODE
App. No. 18/982,656
→
DATA RETENTION READ METHOD
App. No. 18/982,579
→
RECYCLE CURRENT DURING SENSE OF MEMORY CELLS
App. No. 18/982,906
→
METHOD TO ORGANIZE FILE STORAGE BASED ON SEMANTIC SEARCH HISTORY
App. No. 18/983,225
→
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING CAVITY-CONTAINING DIELECTRIC PILLAR STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/980,538
→
POST-ERASE READ OF DUMMY WORD LINE TO SUSTAIN THE SUB-BLOCK MODE DURING UNSELECTED SUB-BLOCK DISTURB
App. No. 18/980,921
→
MANAGING ERASE FAILS DUE TO SINGLE DEFECTIVE WORD LINE
App. No. 18/980,908
→
PROGRAM-VERIFY TECHNIQUES IN A MEMORY DEVICE
App. No. 18/978,534
→
MULTI-PASS PROGRAMMING TECHNIQUES FOR MEMORY DEVICES
App. No. 18/978,514
→
INFERENCE PROCESSING UNIT WITH HIGH BANDWIDTH NON-VOLATILE MEMORY NEAR MEMORY COMPUTING
App. No. 18/977,519
→
VERIFY AND READ CONTROL TECHNIQUES FOR MEMORY DEVICES
App. No. 18/977,479
→
ATS Endpoint Optimization For Storage Workloads
App. No. 18/967,890
→
LOW COMPLEXITY BIT-ERROR-RATE ESTIMATION FOR ENCODED FOGGY-FINE PROGRAMMING
App. No. 18/968,099
→
STACKED MEMORY ASSEMBLY WITH FAILURE DETECTION AND REPAIR
App. No. 18/966,178
→
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING SILICON OXYNITRIDE AND DIPOLE-CONTAINING BLOCKING DIELECTRIC LAYER AND METHODS FOR FORMING THE SAME
App. No. 18/966,778
→
SELF-ALIGNED DIE-TO-WAFER BONDING ARCHITECTURE
App. No. 18/963,996
→
APPARATUS AND METHODS FOR RECOVERING POWER ON READ FAILING DIE
App. No. 18/961,816
→
DIE-TO-WAFER BONDED MEMORY STRUCTURES AND METHODS OF MAKING THE SAME
App. No. 18/959,099
→
DIE-TO-WAFER BONDED MEMORY STRUCTURES AND METHODS OF MAKING THE SAME
App. No. 18/959,002
→
ACTIVATING AUTOMATIC SLEEP AND WAKEUP SEQUENCES IN A NAND DIE BASED ON ANOTHER NAND DIE STATUS
App. No. 18/958,269
→
DIE-TO-WAFER BONDED MEMORY STRUCTURES AND METHODS OF MAKING THE SAME
App. No. 18/959,061
→
COAXIAL WIRE ASSEMBLIES FOR SEMICONDUCTOR PACKAGES
App. No. 18/956,526
→
THREE-DIMENSIONAL MEMORY DEVICE WITH LATERALLY INTEGRATED ACCESS TRANSISTORS AND METHOD OF MAKING THE SAME
App. No. 18/956,635
→
BIO-BASED EPOXY MOLD COMPOUND FOR ELECTRONIC DEVICES
App. No. 18/956,989
→
NON-VOLATILE MEMORY WITH ENHANCED FOGGY-FINE ENCODING
App. No. 18/954,996
→
Data Storage Device with Queue Depth Tracking
App. No. 18/954,923
→
DATA STORAGE DEVICE WITH DUAL MEMORY SPACES ACCESSIBLE BY A HOST USING DIFFERENT COMMUNICATION PROTOCOLS BASED ON THE MATING ORIENTATION OF A REVERSIBLE CONNECTOR
App. No. 18/954,986
→
DATA STORAGE DEVICE WITH DUAL MEMORY SPACES ENABLED BASED ON THE MATING ORIENTATION OF A REVERSIBLE CONNECTOR
App. No. 18/954,904
→
DATA STORAGE DEVICE HAVING A MEMORY BLOCK FAILURE ANTICIPATION SYSTEM
App. No. 18/954,273
→
SEMICONDUCTOR DEVICE INCLUDING LASER BEAM ABSORPTION ENHANCEMENT STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/951,990
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THREE-DIMENSIONAL MEMORY DEVICE CONTAINING CONTOURED SCHOTTKY SOURCE JUNCTIONS AND METHODS FOR FORMING THE SAME
App. No. 18/950,849
→
Authentication of Sanitize Erase
App. No. 18/950,918
→
REVERSE READ WITH LOCKOUT FOR NON-VOLATILE MEMORY
App. No. 18/951,272
→
LOAD BALANCING AMONG DATA STORAGE DEVICES USING REPORTED BANDWIDTH
App. No. 18/950,336
→
Low Power State Staging
App. No. 18/950,564
→
Optimization of an Active Range of mSets Stored in a Compressed Address Table
App. No. 18/950,574
→
THREE-DIMENSIONAL MEMORY DEVICE WITH LOCALIZED ISOLATION TRENCH WIDENING AND METHODS FOR FORMING THE SAME
App. No. 18/949,370
→
ADAPTIVE REPLAY OF PACKETS IN A PERIPHERAL INTERFACE LINK
App. No. 18/949,022
→
Optimized KV Metadata Storage for Machine Learning Applications
App. No. 18/945,856
→
Data Storage Device and Method for Direct Data Quantization in Multi-Level-Cell Memory
App. No. 18/945,932
→
REGION DEPENDENT CURRENT STATE SPACING FOR IN-MEMORY COMPUTE
App. No. 18/945,329
→
SOLAR POWER BASED MEMORY REFRESH IN A DATA STORAGE DEVICE
App. No. 18/943,022
→
ELECTRICAL STRESS DETECTION CIRCUITRY FOR A SEMICONDUCTOR PACKAGE
App. No. 18/943,157
→
DYNAMIC PRIORITY INVERSION FOR HOST MEMORY BUFFER HANDLING BASED ON A SYSTEM STATE
App. No. 18/943,009
→
EXTENDED CONNECTOR CONTACT FOR MEMORY DEVICES
App. No. 18/939,996
→
THREE-DIMENSIONAL MEMORY DEVICE WITH INTEGRATED LINE-AND-VIA STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/940,231
→
Data Storage Device and Method for Selectively Performing a Program-Verify Operation
App. No. 18/939,779
→
HIGH BANDWIDTH BONDED ASSEMBLY WITH THROUGH-SUBSTRATE VIA STRUCTURES SHIELDED BY GUARD RINGS AND METHODS FOR FORMING THE SAME
App. No. 18/940,325
→
Data Storage Device and Method for Value-Proposition-Based Data Retrieval
App. No. 18/938,491
→
Selective Panic Mitigation
App. No. 18/938,733
→
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SILICON OXYCARBIDE LATERAL ETCH-STOP STRUCTURES AND METHODS OF FORMING THE SAME
App. No. 18/937,481
→
Data Storage Device That Detects and Releases Bottlenecks in Hardware
App. No. 18/937,415
→
READ RETRY WITH PHYSICAL DEFECT JUDGEMENT
App. No. 18/935,004
→
PROCESSING CORE INCLUDING HIGH CAPACITY LOW LATENCY STORAGE MEMORY
App. No. 18/933,962
→
Efficient Address Translation Cache Invalidation in Data Storage Devices
App. No. 18/933,321
→
THREE-DIMENSIONAL MEMORY DEVICE WITH SIDE-CONTACT THROUGH-STACK CONTACT VIA STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/933,511
→
BLOCK TO BLOCK TESTING WITH SINGLE SET OF CGI LINES
App. No. 18/933,006
→
BREAKDOWN MITIGATION FOR PROGRAMMABLE RESISTANCE MEMORY ELEMENT
App. No. 18/931,452
→
SEMICONDUCTOR WAFER CONFIGURED FOR SINGLE TOUCH-DOWN TESTING
App. No. 18/930,628
→
APPARATUS AND METHODS FOR STATICALLY MAPPING RANDOM WRITE COMMAND DATA
App. No. 18/925,125
→
TARGETED ENHANCED POST-WRITE READ
App. No. 18/925,222
→