THREE-DIMENSIONAL MEMORY DEVICE WITH LATERALLY INTEGRATED ACCESS TRANSISTORS AND METHOD OF MAKING THE SAME
A device structure includes a three-dimensional array of unit cells. Each of the unit cells includes: an access field effect transistor including a first horizontally-extending semiconductor channel including a first portion of a semiconductor material, a drain region, a first gate dielectric, and a first gate electrode; and a memory field effect transistor including a second horizontally-extending semiconductor channel including a second portion of the semiconductor material, a second gate dielectric, and a second gate electrode. The second gate dielectric includes a memory dielectric material having at least two programmable states.
1 . A device structure comprising a three-dimensional array of unit cells, wherein each of the unit cells comprises:
an access field effect transistor comprising a first horizontally-extending semiconductor channel comprising a first portion of a semiconductor material, a drain region, a first gate dielectric, and a first gate electrode; and
a memory field effect transistor comprising a second horizontally-extending semiconductor channel comprising a second portion of the semiconductor material, a second gate dielectric, and a second gate electrode, wherein the second gate dielectric comprises a memory dielectric material having at least two programmable states.
2 . The device structure of claim 1 , wherein the semiconductor material comprises a polycrystalline semiconductor material.
3 . The device structure of claim 2 , wherein the polycrystalline semiconductor material comprises columnar grains such that an average grain dimension of the columnar grains along a lengthwise direction of the second horizontally-extending semiconductor channel is greater than an average grain dimension of the columnar grains along directions that are perpendicular to the lengthwise direction of the second horizontally-extending semiconductor channel at least by a factor of 2.
4 . The device structure of claim 2 , wherein:
an entirety of the first horizontally-extending semiconductor channel is polycrystalline; and
an entirety of the second horizontally-extending semiconductor channel is polycrystalline.
5 . The device structure of claim 1 , wherein the second portion of the semiconductor material is in contact with a sidewall of the first portion of the semiconductor material.
6 . The device structure of claim 2 , wherein:
the first portion of the semiconductor material includes first electrical dopants of a first conductivity type at a first dopant concentration; and
the second portion of the semiconductor material includes second electrical dopants of the first conductivity type at a second dopant concentration.
7 . The device structure of claim 1 , wherein, within each of the unit cells, the memory field effect transistor comprises a metallic source region in contact with a sidewall of the second horizontally-extending semiconductor channel.
8 . The device structure of claim 7 , wherein the metallic source region comprises a metal-semiconductor alloy of an elemental metal and a semiconductor material of the second horizontally-extending semiconductor channel.
9 . The device structure of claim 7 , wherein the metallic source region comprises a metal silicide material selected from nickel silicide, cobalt silicide, platinum silicide, or palladium silicide.
10 . The device structure of claim 7 , wherein:
the metallic source region has a same vertical extent as the second horizontally-extending semiconductor channel; and
the metallic source region has a same width as the second horizontally-extending semiconductor channel along a horizontal direction that is perpendicular to a lengthwise direction of the second horizontally-extending semiconductor channel.
11 . The device structure of claim 7 , further comprising vertical source lines each contacting sidewalls of a respective vertical stack of metallic source regions of a respective vertical stack of memory field effect transistors.
12 . The device structure of claim 11 , wherein each of the vertical source lines is in contact with a respective subset of the second gate dielectrics within the three-dimensional array of unit cells.
13 . The device structure of claim 1 , wherein, within each of the unit cells:
the first horizontally-extending semiconductor channel has a first uniform vertical extent; and
the second horizontally-extending semiconductor channel has a second uniform vertical extent that is not greater than the first uniform vertical extent.
14 . The device structure of claim 1 , wherein the second gate dielectric comprises a ferroelectric dielectric material.
15 . A method of forming a device structure, comprising:
forming vertically alternating stacks of first material rails including a first material and second material rails including a second material, wherein each of the vertically alternating stacks laterally extends along a first horizontal direction, and the vertically alternating stacks are laterally spaced apart from each other along a second horizontal direction by lateral isolation trenches, and wherein the first material rails either comprise or are replaced with horizontally-extending semiconductor rails;
forming first cavities by removing first portions of the second material rails;
forming first gate dielectrics and first gate electrodes in the first cavities;
forming second cavities by removing second portions of the second material rails; and
forming second gate dielectrics and second gate electrodes in the second cavities, wherein:
an array of unit cells is formed; and
each of the unit cells comprises:
an access field effect transistor comprising a respective one of the first gate dielectrics and a respective one of the first gate electrodes; and
a memory field effect transistor comprising a respective one of the second gate dielectrics and a respective one of the second gate electrodes.
16 . The method of claim 15 , further comprising:
forming laterally-extending cavities by removing the first material rails without removing the second material rails;
forming amorphous semiconductor material rails in the laterally-extending cavities; and
converting the amorphous semiconductor material rails into the horizontally-extending semiconductor rails.
17 . The method of claim 16 , further comprising:
depositing a metal layer on sidewalls of the amorphous semiconductor material rails; and
performing a metal-induced lateral crystallization process in which metal atoms from the metal layer diffuse through the amorphous semiconductor material rails along a horizontal direction to convert the amorphous semiconductor material rails into the horizontally-extending semiconductor rails.
18 . The method of claim 17 , wherein:
the metal atoms accumulate on sidewalls of the horizontally-extending semiconductor rails after the metal-induced lateral crystallization process and form metallic source regions; and
the method further comprises forming vertical source lines such that each of the vertical source lines contacts a vertical stack of a respective subset of the metallic source regions.
19 . The method of claim 17 , wherein an average grain dimension of the columnar grains along a lengthwise direction of the horizontally-extending semiconductor rails is greater than an average grain dimension of the columnar grains along directions that are perpendicular to the lengthwise direction of the horizontally-extending semiconductor rails at least by a factor of 2.
20 . The method of claim 15 , wherein the second gate dielectrics are formed by depositing and patterning a memory dielectric material having at least two programmable states.