Patent Assignment
Reel/Frame 070088/0320
SECURITY AGREEMENT (SUPPLEMENTAL)
Recorded: 2025-02-03
Received: 2025-02-03
Pages: 9
Assignor
SANDISK TECHNOLOGIES, INC.
Executed: 2025-01-31
Assignee
JPMORGAN CHASE BANK, N.A., AS AGENT
10 S. DEARBORN L2, CHICAGO, IL, 60603, UNITED STATES
Covered Applications
(75)
Data Storage Device Holder
App. No. 29/981,741
→
NON-VOLATILE MEMORY WITH SMART TAIL DETECTION READ MODE WITHOUT ERASE TIME PENALTY
App. No. 19/003,033
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Power Consumption Fairness In Multi-Host System
App. No. 19/003,904
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NON-VOLATILE MEMORY WITH DYNAMIC ERASE VOLTAGE
App. No. 19/000,937
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MANAGING POWER STATES IN A DATA STORAGE DEVICE
App. No. 18/989,198
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THERMAL SHUTDOWN HANDLING IN DATA STORAGE DEVICE
App. No. 18/989,133
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SEMICONDUCTOR DEVICE INCLUDING AN ULTRATHIN CONTROLLER DIE
App. No. 18/988,097
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FAILURE DETECTION AND REPAIR CIRCUITS FOR STACKED MEMORY ASSEMBLY
App. No. 18/985,101
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COMBINATION SINGLE-LEVEL CELL PROGRAM MODES TO IMPROVE CELL ENDURANCE
App. No. 18/986,018
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APPARATUS AND METHODS FOR VERTICALLY STACKED INTEGRATED MEMORY ASSEMBLIES
App. No. 18/986,374
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THREE-DIMENSIONAL MEMORY DEVICE INCLUDING SYMMETRIC ARRAY CONNECTION STRIPS AND METHODS FOR FORMING THE SAME
App. No. 18/984,145
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THREE-DIMENSIONAL MEMORY DEVICE INCLUDING SYMMETRIC ARRAY CONNECTION STRIPS AND METHODS FOR FORMING THE SAME
App. No. 18/984,190
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EDGE WORD LINE BIAS ENGINEERING FOR THRESHOLD VOLTAGE MARGIN IMPROVEMENT OF SUB-BLOCK MODE
App. No. 18/982,656
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SEMICONDUCTOR DEVICE INCLUDING VERTICAL WIRE BONDS
App. No. 18/982,848
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CONFIGURABLE INPUT/OUTPUT DRIVER CIRCUITRY FOR CONTROLLER AND NAND COMMUNICATION IN A DATA STORAGE DEVICE
App. No. 18/983,213
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DATA RETENTION READ METHOD
App. No. 18/982,579
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RECYCLE CURRENT DURING SENSE OF MEMORY CELLS
App. No. 18/982,906
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METHOD TO ORGANIZE FILE STORAGE BASED ON SEMANTIC SEARCH HISTORY
App. No. 18/983,225
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POST-ERASE READ OF DUMMY WORD LINE TO SUSTAIN THE SUB-BLOCK MODE DURING UNSELECTED SUB-BLOCK DISTURB
App. No. 18/980,921
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THREE-DIMENSIONAL MEMORY DEVICE INCLUDING CAVITY-CONTAINING DIELECTRIC PILLAR STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/980,538
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MANAGING ERASE FAILS DUE TO SINGLE DEFECTIVE WORD LINE
App. No. 18/980,908
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MULTI-PASS PROGRAMMING TECHNIQUES FOR MEMORY DEVICES
App. No. 18/978,514
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PROGRAM-VERIFY TECHNIQUES IN A MEMORY DEVICE
App. No. 18/978,534
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INFERENCE PROCESSING UNIT WITH HIGH BANDWIDTH NON-VOLATILE MEMORY NEAR MEMORY COMPUTING
App. No. 18/977,519
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VERIFY AND READ CONTROL TECHNIQUES FOR MEMORY DEVICES
App. No. 18/977,479
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ATS Endpoint Optimization For Storage Workloads
App. No. 18/967,890
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LOW COMPLEXITY BIT-ERROR-RATE ESTIMATION FOR ENCODED FOGGY-FINE PROGRAMMING
App. No. 18/968,099
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STACKED MEMORY ASSEMBLY WITH FAILURE DETECTION AND REPAIR
App. No. 18/966,178
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THREE-DIMENSIONAL MEMORY DEVICE INCLUDING SILICON OXYNITRIDE AND DIPOLE-CONTAINING BLOCKING DIELECTRIC LAYER AND METHODS FOR FORMING THE SAME
App. No. 18/966,778
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SELF-ALIGNED DIE-TO-WAFER BONDING ARCHITECTURE
App. No. 18/963,996
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APPARATUS AND METHODS FOR RECOVERING POWER ON READ FAILING DIE
App. No. 18/961,816
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DIE-TO-WAFER BONDED MEMORY STRUCTURES AND METHODS OF MAKING THE SAME
App. No. 18/959,099
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DIE-TO-WAFER BONDED MEMORY STRUCTURES AND METHODS OF MAKING THE SAME
App. No. 18/959,061
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ACTIVATING AUTOMATIC SLEEP AND WAKEUP SEQUENCES IN A NAND DIE BASED ON ANOTHER NAND DIE STATUS
App. No. 18/958,269
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DIE-TO-WAFER BONDED MEMORY STRUCTURES AND METHODS OF MAKING THE SAME
App. No. 18/959,002
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COAXIAL WIRE ASSEMBLIES FOR SEMICONDUCTOR PACKAGES
App. No. 18/956,526
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THREE-DIMENSIONAL MEMORY DEVICE WITH LATERALLY INTEGRATED ACCESS TRANSISTORS AND METHOD OF MAKING THE SAME
App. No. 18/956,635
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BIO-BASED EPOXY MOLD COMPOUND FOR ELECTRONIC DEVICES
App. No. 18/956,989
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NON-VOLATILE MEMORY WITH ENHANCED FOGGY-FINE ENCODING
App. No. 18/954,996
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Data Storage Device with Queue Depth Tracking
App. No. 18/954,923
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DATA STORAGE DEVICE WITH DUAL MEMORY SPACES ACCESSIBLE BY A HOST USING DIFFERENT COMMUNICATION PROTOCOLS BASED ON THE MATING ORIENTATION OF A REVERSIBLE CONNECTOR
App. No. 18/954,986
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DATA STORAGE DEVICE WITH DUAL MEMORY SPACES ENABLED BASED ON THE MATING ORIENTATION OF A REVERSIBLE CONNECTOR
App. No. 18/954,904
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DATA STORAGE DEVICE HAVING A MEMORY BLOCK FAILURE ANTICIPATION SYSTEM
App. No. 18/954,273
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SEMICONDUCTOR DEVICE INCLUDING LASER BEAM ABSORPTION ENHANCEMENT STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/951,990
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THREE-DIMENSIONAL MEMORY DEVICE CONTAINING CONTOURED SCHOTTKY SOURCE JUNCTIONS AND METHODS FOR FORMING THE SAME
App. No. 18/950,849
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Optimization of an Active Range of mSets Stored in a Compressed Address Table
App. No. 18/950,574
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Low Power State Staging
App. No. 18/950,564
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REVERSE READ WITH LOCKOUT FOR NON-VOLATILE MEMORY
App. No. 18/951,272
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Authentication of Sanitize Erase
App. No. 18/950,918
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LOAD BALANCING AMONG DATA STORAGE DEVICES USING REPORTED BANDWIDTH
App. No. 18/950,336
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ADAPTIVE REPLAY OF PACKETS IN A PERIPHERAL INTERFACE LINK
App. No. 18/949,022
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THREE-DIMENSIONAL MEMORY DEVICE WITH LOCALIZED ISOLATION TRENCH WIDENING AND METHODS FOR FORMING THE SAME
App. No. 18/949,370
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Data Storage Device and Method for Direct Data Quantization in Multi-Level-Cell Memory
App. No. 18/945,932
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Optimized KV Metadata Storage for Machine Learning Applications
App. No. 18/945,856
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REGION DEPENDENT CURRENT STATE SPACING FOR IN-MEMORY COMPUTE
App. No. 18/945,329
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DYNAMIC PRIORITY INVERSION FOR HOST MEMORY BUFFER HANDLING BASED ON A SYSTEM STATE
App. No. 18/943,009
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SOLAR POWER BASED MEMORY REFRESH IN A DATA STORAGE DEVICE
App. No. 18/943,022
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ELECTRICAL STRESS DETECTION CIRCUITRY FOR A SEMICONDUCTOR PACKAGE
App. No. 18/943,157
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HIGH BANDWIDTH BONDED ASSEMBLY WITH THROUGH-SUBSTRATE VIA STRUCTURES SHIELDED BY GUARD RINGS AND METHODS FOR FORMING THE SAME
App. No. 18/940,325
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EXTENDED CONNECTOR CONTACT FOR MEMORY DEVICES
App. No. 18/939,996
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THREE-DIMENSIONAL MEMORY DEVICE WITH INTEGRATED LINE-AND-VIA STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/940,231
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Data Storage Device and Method for Selectively Performing a Program-Verify Operation
App. No. 18/939,779
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Selective Panic Mitigation
App. No. 18/938,733
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Data Storage Device and Method for Value-Proposition-Based Data Retrieval
App. No. 18/938,491
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THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SILICON OXYCARBIDE LATERAL ETCH-STOP STRUCTURES AND METHODS OF FORMING THE SAME
App. No. 18/937,481
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Data Storage Device That Detects and Releases Bottlenecks in Hardware
App. No. 18/937,415
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READ RETRY WITH PHYSICAL DEFECT JUDGEMENT
App. No. 18/935,004
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PROCESSING CORE INCLUDING HIGH CAPACITY LOW LATENCY STORAGE MEMORY
App. No. 18/933,962
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Efficient Address Translation Cache Invalidation in Data Storage Devices
App. No. 18/933,321
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THREE-DIMENSIONAL MEMORY DEVICE WITH SIDE-CONTACT THROUGH-STACK CONTACT VIA STRUCTURES AND METHODS FOR FORMING THE SAME
App. No. 18/933,511
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BLOCK TO BLOCK TESTING WITH SINGLE SET OF CGI LINES
App. No. 18/933,006
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BREAKDOWN MITIGATION FOR PROGRAMMABLE RESISTANCE MEMORY ELEMENT
App. No. 18/931,452
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SEMICONDUCTOR WAFER CONFIGURED FOR SINGLE TOUCH-DOWN TESTING
App. No. 18/930,628
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APPARATUS AND METHODS FOR STATICALLY MAPPING RANDOM WRITE COMMAND DATA
App. No. 18/925,125
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TARGETED ENHANCED POST-WRITE READ
App. No. 18/925,222
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