MULTI-PASS PROGRAMMING TECHNIQUES FOR MEMORY DEVICES
The memory device includes a plane with memory blocks, each with an array of memory cells that are arranged in word lines. The memory device also includes programming circuitry that is configured to, in a selected memory block, program foggy data into the memory cells of a selected word line in a first programming pass. The circuitry is also configured to, in at least one parity memory block of the plurality of memory blocks, program two bits of parity data. The circuitry is further configured to read the foggy data of the memory cells of the selected word line of the selected memory block and read the parity data of the at least one parity memory block to reconstruct user data. The circuitry is also configured to perform a second programming pass on the selected word line.
1 . A method of programming a memory device, comprising the steps of:
preparing a plurality of memory blocks, each of the memory blocks including an array of memory cells that are arranged in a plurality of word lines;
in a selected memory block of the plurality of memory blocks, programming foggy data into the memory cells of a selected word line of the plurality of word lines in a first programming pass;
in at least one parity memory block of the plurality of memory blocks, programming two bits of parity data;
reading the foggy data of the memory cells of the selected word line of the selected memory block and reading the parity data of the at least one parity memory block to reconstruct user data; and
performing a second programming pass on the selected word line of the selected memory block.
2 . The method as set forth in claim 1 , wherein the parity data is stored in a two-bits per memory cell storage format.
3 . The method as set forth in claim 2 , wherein the step of programming the two bits of parity data to the at least one parity memory block includes programming the two bits of parity data in a programming operation that includes three programming pulses and no verify operations.
4 . The method as set forth in claim 1 , wherein the user data includes at least fifteen programmed data states.
5 . The method as set forth in claim 4 , wherein the foggy data includes at least twelve programmed data states.
6 . The method as set forth in claim 5 , wherein the step of programming the foggy data into the memory cells of the selected word line includes verify operations for a plurality of checkpoint data states that is fewer than the at least twelve data states and skipping verify operations for a plurality of non-checkpoint data states.
7 . The method as set forth in claim 6 , wherein the plurality of checkpoint data states includes four of the at least twelve programmed data states.
8 . The method as set forth in claim 7 , wherein the plurality of checkpoint data states includes three of the at least twelve programmed data states.
9 . A memory device, comprising:
a plane including a plurality of memory blocks, each of the memory blocks including an array of memory cells that are arranged in a plurality of word lines;
programming circuitry that is configured to:
in a selected memory block of the plurality of memory blocks, program foggy data into the memory cells of a selected word line of the plurality of word lines in a first programming pass;
in at least one parity memory block of the plurality of memory blocks, program two bits of parity data;
read the foggy data of the memory cells of the selected word line of the selected memory block and read the parity data of the at least one parity memory block to reconstruct user data; and
perform a second programming pass on the selected word line of the selected memory block.
10 . The memory device as set forth in claim 9 , wherein the parity data is stored by the programming circuitry in a two-bits per memory cell storage format.
11 . The memory device as set forth in claim 10 , wherein when the programming circuitry programs the two bits of parity data to the at least one parity memory block, the programming circuitry performs a programming operation that includes three programming pulses and no verify operations.
12 . The memory device as set forth in claim 9 , wherein the user data includes at least fifteen programmed data states.
13 . The memory device as set forth in claim 12 , wherein the foggy data includes at least twelve programmed data states.
14 . The memory device as set forth in claim 13 , wherein during programming of the foggy data into the memory cells of the selected word line, the programming circuitry performs verify operations for a plurality of checkpoint data states that is fewer than the at least twelve data states and skipping verify operations for a plurality of non-checkpoint data states.
15 . The memory device as set forth in claim 14 , wherein the plurality of checkpoint data states includes no greater than four of the at least twelve programmed data states.
16 . The memory device as set forth in claim 15 , wherein the plurality of checkpoint data states includes no greater than three of the at least twelve programmed data states.
17 . An apparatus, comprising:
a plurality of memory blocks, each of the memory blocks including an array of memory cells that are arranged in a plurality of word lines;
a programming means for programming user data into the memory cells of a selected word line in a selected memory block, the programming means being configured to:
in the selected memory block, program foggy data into the selected word line of in a foggy programming pass;
in at least one parity memory block of the plurality of memory blocks, program two bits of parity data;
read the foggy data of the memory cells of the selected word line of the selected memory block and read the parity data of the at least one parity memory block to reconstruct the user data; and
perform a second programming pass on the selected word line of the selected memory block.
18 . The apparatus as set forth in claim 17 , wherein the parity data is stored by the programming circuitry in a two-bits per memory cell storage format.
19 . The apparatus as set forth in claim 18 , wherein when the programming means programs the two bits of parity data to the at least one parity memory block, the programming means performs a programming operation that includes three programming pulses and no verify operations.
20 . The apparatus as set forth in claim 18 , wherein the user data includes at least fifteen programmed data states.