Authentication of Sanitize Erase
Adding a bypass module and a pattern detector module to a data path of a controller will increase the efficiency of both sanitize block erase audit and sanitize crypto erase audit operations. The sanitize crypto erase audit skips an end to end (E 2 E) protection module to provide decrypted data to a static random access memory (SRAM) buffer and ultimately a host device through a direct memory access (DMA) module. The sanitize block erase audit utilizes the pattern detector module to provide a known pattern to the SRAM buffer and host through the DMA module. The bypass module and pattern detector module feed into a multiplexer (Mux) prior to the SRAM buffer.
1 . A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller comprises a bypass module, an end to end (E2E) protection module, and a pattern detector module in a data path, wherein the controller is configured to perform a sanitize crypto erase audit comprising:
reading data from the memory device;
storing the read data in a buffer;
performing error correction on the read data;
decrypting the read data;
bypassing the E2E protection module;
storing the data in volatile memory; and
delivering the data to a host device.
2 . The data storage device of claim 1 , wherein the controller comprises a key module for storing crypto keys.
3 . The data storage device of claim 2 , wherein the controller includes a central processing unit (CPU) and wherein the CPU is configured to trigger the data path of the controller.
4 . The data storage device of claim 3 , wherein the CPU is also configured to instruct the CPU to delete the crypto keys stored in the key module during a sanitize crypto erase operation.
5 . The data storage device of claim 3 , wherein the CPU is also configured to set the pattern detector module to active.
6 . The data storage device of claim 1 , wherein the controller comprises one or more of a direct memory access module (DMA), a first SRAM buffer, a multiplexer (Mux), an error correction module, a second SRAM buffer, a flash interface module (FIM), and an encryption (XTS) module.
7 . The data storage device of claim 1 , wherein the crypto erase audit occurs after a sanitize crypto erase operation.
8 . A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller comprises a bypass module and a pattern matcher module, wherein the controller is configured to:
read data from the memory device;
determine that the read data is a known pattern;
store the read data in static random access memory (SRAM) buffer; and
pass the read data to a host device.
9 . The data storage device of claim 8 , wherein the controller is configured to set the bypass module to active after instructing a central processing unit (CPU) to delete crypto keys.
10 . The data storage device of claim 8 , wherein the controller includes a central processing unit (CPU) and wherein the CPU is configured to trigger a data path of the controller.
11 . The data storage device of claim 10 , wherein the CPU is also configured to delete crypto keys in a keys module of a data path of the controller.
12 . The data storage device of claim 10 , wherein the CPU is also configured to set the bypass module to active.
13 . The data storage device of claim 8 , wherein the controller comprises one or more of a direct memory access module (DMA), a multiplexer (Mux), an end to end (E2E) protection module, and an encryption (XTS) module, and wherein the bypass module is coupled between the XTS module and the Mux.
14 . The data storage device of claim 8 , wherein controller is configured to:
emulate an end to end (E2E) error upon determining that data does not match a known pattern; and
deliver a command completion with error to a host device.
15 . A data storage device, comprising:
means for storing data; and
a controller coupled to the means for storing data, wherein the controller comprises:
a control path comprising a central processing unit (CPU) and an audit mode module; and
a data path comprising a static random access memory (SRAM) buffer; a multiplexer (Mux) coupled to the SRAM buffer and the audit mode module, a bypass module coupled to the Mux, and a pattern detector module coupled to the Mux, wherein the controller is configured to perform a pattern detection operation in a sanitize block erase audit mode or a bypass of a E2E module in a sanitize crypto erase audit mode.
16 . The data storage device of claim 15 , wherein the bypass module and the Mux are configured to be used during the sanitize crypto erase audit.
17 . The data storage device of claim 16 , wherein during the crypto erase audit, results produced by the E2E module are bypassed using the bypass module and Mux.
18 . The data storage device of claim 15 , wherein the pattern detector module and the Mux are configured to be used during the sanitize block erase audit.
19 . The data storage device of claim 18 , wherein during the sanitize block erase audit, the pattern detector module is configured to determine whether a successful erase block pattern matching has occurred.
20 . The data storage device of claim 19 , wherein the controller is configured to emulate an E2E error upon determining that the erase block pattern matching was not successful.