Apparatus and methods for statically mapping random write command data
An apparatus includes a memory array including blocks of non-volatile memory cells and a control circuit coupled to the memory array. The control circuit is configured to receive first write commands, determine that the first write commands satisfy predetermined criteria, and process the first write commands by: statically mapping the logical block addresses to corresponding physical block addresses of first ones of the blocks of non-volatile memory cells, and writing data from the first write commands to the first ones of the blocks.
1 . An apparatus comprising:
a memory array comprising blocks of non-volatile memory cells; and
a control circuit coupled to the memory array, the control circuit configured to:
receive a first plurality of write commands;
determine that the first plurality of write commands satisfies predetermined criteria of only non-overlapping random write commands;
process the first plurality of write commands that satisfies the predetermine criteria by:
statically mapping the logical block addresses to corresponding physical block addresses of a first plurality of the blocks of non-volatile memory cells; and
writing data from the first plurality of write commands to the first plurality of blocks.
2 . The apparatus of claim 1 , wherein the first plurality of write commands comprise random write commands.
3 . The apparatus of claim 1 , wherein each of the first plurality of write commands comprise less than a page of data.
4 . The apparatus of claim 1 , wherein the control circuit is further configured to determine a range of logical block addresses in the first plurality of write commands.
5 . The apparatus of claim 4 , wherein the control circuit is further configured to determine a number of a blocks needed to store data of the determined range of logical block addresses, wherein each block comprises memory cells configured to store one bit of data per memory cell.
6 . The apparatus of claim 1 , wherein determining that the first plurality of write commands satisfies predetermined criteria comprises determining that the first plurality of write commands comprise non-repeating, non-overlapping write commands.
7 . The apparatus of claim 1 , wherein the first plurality of the blocks comprise memory cells configured to store one bit of data per memory cell.
8 . The apparatus of claim 1 , wherein the first plurality of the blocks comprise memory cells that may store more than one bit of data per memory cell, but the control circuit is configured to store only one bit of data per memory cell in the first plurality of the blocks.
9 . The apparatus of claim 1 , wherein the control circuit is further configured to write data to the first plurality of blocks using partial page programming.
10 . The apparatus of claim 1 , wherein the control circuit is further configured to write data to the first plurality of blocks using a one-to-one mapping of logical block addresses to corresponding block offsets.
11 . The apparatus of claim 1 , wherein the control circuit is further configured to:
receive a second plurality of write commands;
determine that the second plurality of write commands does not satisfy the predetermined criteria;
write data from the second plurality of write commands to sequential blocks of non-volatile memory cells; and
create entries corresponding to the second plurality of write commands in a logical to physical address mapping table.
12 . An apparatus comprising:
a memory array comprising non-volatile memory cells; and
a control circuit coupled to the memory array, the control circuit configured to:
receive a plurality of random write commands of only non-overlapping random write commands;
determine a range of logical block addresses in the random write commands;
determine a number of a blocks needed to store data of the random write commands, wherein each block comprises memory cells configured to store one bit of data per memory cell;
simultaneously open the determined number of blocks;
statically map the logical block addresses to corresponding physical block addresses of the opened blocks of non-volatile memory cells; and
write data from the random write commands to non-sequential flash management units in the opened blocks.
13 . The apparatus of claim 12 , wherein the control circuit is further configured to prevent relocation of data in the opened blocks.
14 . The apparatus of claim 12 , wherein the control circuit is further configured to close all of the opened blocks after completing writing data from the random write commands.
15 . The apparatus of claim 14 , wherein the control circuit is further configured to allow relocation of data in the closed blocks.
16 . The apparatus of claim 12 , wherein the plurality of random write commands comprise non-repeating, non-overlapping random write commands.
17 . The apparatus of claim 12 , wherein the control circuit is further configured to write data to the opened blocks using partial page programming.
18 . The apparatus of claim 12 , wherein the control circuit is further configured to write data from the random write commands to the memory array without updating a logical to physical address mapping table.
19 . A method comprising:
receiving a plurality of write commands at a control circuit coupled to a NAND memory array, each write command comprising a corresponding logical block address;
determining that the plurality of write commands of only non-repeating, non-overlapping random write commands;
determining a range of the corresponding logical block addresses of the plurality of write commands;
simultaneously opening a plurality of blocks to store data of the plurality of write commands, each block comprising NAND memory cells each configured to store one bit of data; and
writing the data of the plurality of write commands to the plurality of opened blocks using partial page programming,
wherein the data are written without updating a logical to physical address map for the NAND memory array.