Translation And Data Management In Storage Devices
With ever-increasing capacities and performance demanded in new storage devices, the number of control table data entries are increased to store more updates stemming from the increased number of read and/or write operations. To avoid becoming a bottleneck, devices, such as storage devices, and other similar methods and systems as described herein efficiently manage control table sets to reduce latency. This can be accomplished by designating a specific position for each control table set and storing updates to such control table sets in a designated position. Furthermore, data can be efficiently kept in the volatile memory, such as SRAM, or evicted from the volatile memory to the non-volatile memory, such as NAND. Determinations can occur for when the read/write operations should be performed using volatile memory or non-volatile memory. These determinations can be decided dynamically and based on the storage device state and incoming workload, resulting in lower overall latencies.
1 . A storage device, including:
a processor;
a memory array comprising a plurality of memory devices, wherein the plurality of memory devices is configured to store a plurality of control table sets; and
a control table set management logic configured to:
receive a read command from a host device associated with logical to physical address mapping updates;
determine a control table set of the plurality of control table sets associated with the read command;
determine a first search time based on a number of data entries for a range of data associated with the determined control table set of the plurality of control table sets;
determine a second search time based on an amount of data entries in each of the control table sets of the plurality of control table sets; and
upon a determination that the first and second search time does not exceed a first and second threshold, respectively, perform a read operation in an upload layer of the storage device.
2 . The storage device of claim 1 , wherein the storage portion of the host device is a cache memory.
3 . The storage device of claim 2 , wherein the cache memory of the host device is accessible by the storage device.
4 . The device of claim 1 , wherein the storage device can access the cache memory via a PCIe interface.
5 . The device of claim 1 , wherein the control table set management logic is configured to:
receive a second command from the host device, wherein the second command is associated with the logical to physical address mapping updates, wherein the second command is a write command.
6 . The device of claim 5 , wherein the control table set management logic is configured to:
upon a determination that the first and second search time exceeds the first and second threshold, respectively, perform the read operation in the storage portion of the host device.
7 . The storage device of claim 1 , wherein the plurality of memory devices includes non-volatile memory devices.
8 . The device of claim 7 , wherein the non-volatile memory devices include NAND devices.
9 . The device of claim 5 , wherein the control table set management logic is configured to:
perform the read operation in the plurality of memory devices if the first command is written sequentially.
10 . The device of claim 6 , wherein the control table set management logic is configured to:
perform the read operation in the storage portion of the host device if the first command is written randomly.
11 . The device of claim 1 , wherein the control table set management logic is configured to:
update the storage portion of the host device by storing missing copies of received commands into the storage portion.
12 . The device of claim 11 , wherein the control table set management logic updates the storage portion of the host device when a host device processor is idle.
13 . The device of claim 11 , wherein the control table set management logic is configured to:
determine an average search time based on the number of data entries for a given range.
14 . The device of claim 1 , wherein each of the plurality of control table sets is configured to store a distinct range of logical to physical address mapping data entries.
15 . A method for decreasing latency in a memory device, the method comprising:
receiving a read command from a host device that is associated with logical to physical address mapping updates;
determining a control table set among a plurality of control table sets associated with the read command;
determining an average search time based on a number of data entries for a range of data associated with the determined control table set, and an amount of data entries in each of the plurality of control table sets;
upon a determination that the average search time does not exceed a threshold, perform a read operation in an upload layer of the memory device.
16 . The method of claim 15 , further comprising:
receiving a write command from the host device that is associated with the logical to physical address mapping updates.
17 . The method of claim 16 , further comprising:
upon a determination that the search time exceeds the threshold, performing the read operation in the cache memory of the host device.
18 . The method of claim 15 , further comprising:
performing the read operation in the memory device if the first command is written sequentially; and
performing the read operation in the storage portion of the host device if the first command is written randomly.
19 . The method of claim 15 , further comprising:
updating the cache memory of the host device by storing missing copies of received commands into the cache memory.
20 . A non-transitory machine-readable medium having instructions stored therein, which when executed by a processor, direct the processor to perform operations comprising:
receiving a first command from a host device, wherein the first command is associated with logical to physical address mapping updates, wherein the first command comprises a read command;
determining a control table set among a plurality of control table sets associated with the first command;
determining a search time based on a number of data entries for a range of data associated with the determined control table set, and an amount of data entries in each of the plurality of control table sets;
upon a first determination that the search time does not exceed a threshold, storing the first command in the memory device;
upon a second determination that the search time exceeds the threshold, accessing a cache memory of the host device;
storing the first command in the accessed cache memory; and
upon a third determination that the search time does not exceed the threshold, performing a read operation in the memory device.