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App. No. 19/014,638 · Confirmation No. 2469

MITIGATION FOR CAPACITIVE COUPLING IN ELECTRICAL PATHWAYS IN NON-VOLATILE MEMORY DIES

Inventor: Jayavel Pachamuthu
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2026-07-10 NTC.PUB Notice of Publication 1 View
2025-01-29 WFEE Fee Worksheet (SB06) 1 View
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2025-01-29 WELCOME.LET Welcome Letter from USPTO Director and Deputy Director 1 View
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2025-01-09 IDS Information Disclosure Statement (IDS) Form (SB08) 4 View
2025-01-09 SPEC Specification 34 View
2025-01-09 CLM Claims 4 View
2025-01-09 ABST Abstract 1 View
2025-01-09 ADS Application Data Sheet 8 View
2025-01-09 OATH Oath or Declaration filed 2 View
2025-01-09 DRW.NONBW Drawings-other than black and white line drawings 28 View
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2025-01-09 SCORE Placeholder sheet indicating presence of supplemental content in Supplemental Complex Repository for Examiners(SCORE) 1 View
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Quick Facts
App. No.
19/014,638
Filed
2025-01-09
Pub. No.
US20260195259A1
Art Unit
OPAP