SEMICONDUCTOR DEVICE INCLUDING AN INTEGRATED TIM-ON-DIE
A semiconductor controller includes a controller semiconductor die having an integrated thermal interface material layer, or TIM formed on top of the die. In embodiments, the controller semiconductor die may be mounted on a substrate, for example in a flip-chip configuration. Thereafter, the TIM may be positioned on an upper surface of the controller semiconductor die and the TIM and controller semiconductor die may be positioned within a mold chase for encapsulation in mold compound. After encapsulation, the TIM may be exposed in an upper surface of the encapsulated controller semiconductor die.
1 . A semiconductor controller, comprising:
a substrate;
a controller semiconductor die physically and electrically mounted to the substrate;
a thermal interface material (TIM) layer comprising first and second opposed surfaces, the first surface of the TIM layer affixed to a surface of the controller semiconductor die, the TIM layer configured to conduct heat away from the controller semiconductor die; and
an encapsulant for at least partially encapsulating the semiconductor controller, wherein the second surface of the TIM layer is exposed through the encapsulant.
2 . The semiconductor controller of claim 1 , wherein the controller semiconductor die is flip-chip mounted to the substrate by a plurality of solder balls.
3 . The semiconductor controller of claim 1 , wherein the TIM layer is comprised of a plurality of sublayers.
4 . The semiconductor controller of claim 3 , wherein a first sublayer of the TIM layer is comprised of Copper.
5 . The semiconductor controller of claim 4 , wherein a second sublayer of the TIM layer is comprised of one of a thermally conductive adhesive and a thermally conductive solder mask.
6 . The semiconductor controller of claim 5 , wherein a third sublayer of the TIM layer is comprised of Nickel and a fourth sublayer of the TIM layer is comprised of Chromium.
7 . The semiconductor controller of claim 1 , wherein the encapsulant is applied to the controller semiconductor die after the TIM layer is affixed to the controller semiconductor die.
8 . The semiconductor controller of claim 1 , wherein the encapsulant forms a border around at least one side of the exposed second surface of the TIM layer.
9 . The semiconductor controller of claim 1 , wherein the exposed second surface of the TIM layer forms the entire upper surface of the semiconductor controller.
10 . The semiconductor controller of claim 1 , wherein the encapsulant is mold compound applied using a pair of mold plates.
11 . The semiconductor controller of claim 1 , wherein the semiconductor controller is one of a plurality of semiconductor controllers formed on a panel, wherein the TIM layer is applied as a sheet over all of the plurality of semiconductor controllers on the panel.
12 . The semiconductor controller of claim 1 , wherein the TIM layer is singulated from the panel with the controller semiconductor die.
13 . The semiconductor controller of claim 1 , wherein the semiconductor controller is an ASIC.
14 . The semiconductor controller of claim 1 , wherein the semiconductor controller is a specialized processor comprising one of a graphics processing unit and an artificial intelligence processing unit.
15 . A semiconductor memory package, comprising:
a first substrate;
one or more semiconductor memory dies physically and electrically coupled to the first substrate; and
a semiconductor controller for controlling operation of the one or more semiconductor memory dies, the semiconductor controller comprising:
a second substrate;
a controller semiconductor die physically and electrically mounted to the second substrate;
a thermal interface material (TIM) layer comprising first and second opposed surfaces, the first surface of the TIM layer affixed to a surface of the controller semiconductor die, the TIM layer configured to conduct heat away from the controller semiconductor die; and
an encapsulant for at least partially encapsulating the semiconductor controller, wherein the second surface of the TIM layer is exposed through the encapsulant.
16 . The semiconductor memory package of claim 15 , wherein the encapsulant comprises a first encapsulant, the semiconductor memory package further comprising a second encapsulant around the controller semiconductor die and the one or more memory dies, wherein the second surface of the TIM layer is exposed through the second encapsulant.
17 . The semiconductor memory package of claim 15 , wherein the TIM layer is comprised of a plurality of sublayers of different materials.
18 . The semiconductor controller of claim 15 , wherein the encapsulant is applied to the controller semiconductor die after the TIM layer is directly affixed to the controller semiconductor die.
19 . The semiconductor controller of claim 15 , wherein the encapsulant forms a border around at least one side of the exposed second surface of the TIM layer.
20 . A semiconductor controller, comprising:
a substrate;
a controller semiconductor die physically and electrically mounted to the substrate;
thermal interface means, connected to the controller semiconductor die, for conducting heat away from the controller semiconductor die; and
an encapsulant for at least partially encapsulating the semiconductor controller, wherein a portion of the thermal interface means is exposed through the encapsulant.