COUNTERMEASURE FOR DRAIN-SIDE SELECT GATE UPPER TAIL

1 . A memory apparatus, comprising:

drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage; and

a control means configured to:

perform a predetermined quantity of erase operations on the memory cells of at least one block of a die of the memory cells, and

report the die as failing in response to determining the transistor threshold voltage of one or more of the drain-side select gate transistors of the at least one block does not meet a predetermined criteria.

2 . The memory apparatus as set forth in claim 1 , wherein the predetermined criteria is at least one predetermined failure quantity the drain-side select gate transistors of the at least one block having the transistor threshold voltage above at least one predetermined transistor threshold voltage.

3 . The memory apparatus as set forth in claim 2 , wherein the at least one predetermined transistor threshold voltage includes a first predetermined transistor threshold voltage and a second predetermined transistor threshold voltage, the at least one predetermined failure quantity includes a first predetermined failure quantity and a second predetermined failure quantity, and the control means is further configured to:

read the drain-side select gate transistors of the at least one block using the first predetermined transistor threshold voltage and count a first actual quantity of the drain-side select gate transistors of the at least one block having the transistor threshold voltage above the first predetermined transistor threshold voltage;

read the drain-side select gate transistors of the at least one block using the second predetermined transistor threshold voltage and count a second actual quantity of the drain-side select gate transistors of the at least one block having the transistor threshold voltage above the first predetermined transistor threshold voltage; and

report the die as failing in response to determining at least one of the first actual quantity of the drain-side select gate transistors of the at least one block having the transistor threshold voltage above the first predetermined transistor threshold voltage exceeds at least one of the first predetermined failure quantity and the second predetermined failure quantity or the second actual quantity of the drain-side select gate transistors of the at least one block having the transistor threshold voltage above the second predetermined transistor threshold voltage exceeds the second predetermined failure quantity.

4 . The memory apparatus as set forth in claim 2 , wherein the at least one block includes a plurality of sample blocks and the control means is further configured, for each of the plurality of sample blocks, to:

determine the transistor threshold voltage of the drain-side select gate transistors of one of the plurality of sample blocks;

perform the predetermined quantity of erase operations on the one of the plurality of sample blocks of the die of the memory cells;

read the drain-side select gate transistors of the one of the plurality of sample blocks using the at least one predetermined transistor threshold voltage and count at least one actual quantity of the drain-side select gate transistors of the one of the plurality of sample blocks having the transistor threshold voltage above the at least one predetermined transistor threshold voltage;

determine whether the at least one actual quantity of the drain-side select gate transistors of the one of the plurality of sample blocks having the transistor threshold voltage above the at least one predetermined transistor threshold voltage exceeds the at least one predetermined failure quantity;

return to determining the transistor threshold voltage of the drain-side select gate transistors of the one of the plurality of sample blocks for a next one of the plurality of sample blocks in response to determining the at least one actual quantity of the drain-side select gate transistors of the one of the plurality of sample blocks having the transistor threshold voltage above the at least one predetermined transistor threshold voltage does not exceed the at least one predetermined failure quantity; and

report the die as failing in response to determining the at least one actual quantity of the drain-side select gate transistors of the one of the plurality of sample blocks having the transistor threshold voltage above the at least one predetermined transistor threshold voltage exceeds the at least one predetermined failure quantity.

5 . The memory apparatus as set forth in claim 1 , wherein the memory cells are each connected to one of a plurality of word lines and the control means is further configured, immediately before each of the predetermined quantity of erase operations, to apply a pre-program pulse of a pre-program voltage to all of the plurality of word lines of the at least one block being erased, the pre-program voltage selected to shift the memory cells of the at least one block being erased towards a uniform threshold voltage distribution.

6 . The memory apparatus as set forth in claim 1 , wherein the die has a three dimensional quadrilateral shape and defines eight corners, the at least one block includes a plurality of sample blocks each disposed at one or more of the eight corners of the die.

7 . The memory apparatus as set forth in claim 1 , wherein the predetermined quantity of erase operations is approximately 20000 erase operations.

8 . A controller in communication with a memory apparatus including drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage, the controller configured to:

instruct the memory apparatus to perform a predetermined quantity of erase operations on the memory cells of at least one block of a die of the memory cells; and

report the die as failing in response to determining the transistor threshold voltage of one or more of the drain-side select gate transistors of the at least one block does not meet a predetermined criteria.

9 . The controller as set forth in claim 8 , wherein the predetermined criteria is at least one predetermined failure quantity the drain-side select gate transistors of the at least one block having the transistor threshold voltage above at least one predetermined transistor threshold voltage.

10 . The controller as set forth in claim 9 , wherein the at least one predetermined transistor threshold voltage includes a first predetermined transistor threshold voltage and a second predetermined transistor threshold voltage, the at least one predetermined failure quantity includes a first predetermined failure quantity and a second predetermined failure quantity, and the controller is further configured to:

instruct the memory apparatus to read the drain-side select gate transistors of the at least one block using the first predetermined transistor threshold voltage and count a first actual quantity of the drain-side select gate transistors of the at least one block having the transistor threshold voltage above the first predetermined transistor threshold voltage;

instruct the memory apparatus to read the drain-side select gate transistors of the at least one block using the second predetermined transistor threshold voltage and count a second actual quantity of the drain-side select gate transistors of the at least one block having the transistor threshold voltage above the first predetermined transistor threshold voltage; and

report the die as failing in response to determining at least one of the first actual quantity of the drain-side select gate transistors of the at least one block having the transistor threshold voltage above the first predetermined transistor threshold voltage exceeds at least one of the first predetermined failure quantity and the second predetermined failure quantity or the second actual quantity of the drain-side select gate transistors of the at least one block having the transistor threshold voltage above the second predetermined transistor threshold voltage exceeds the second predetermined failure quantity.

11 . The controller as set forth in claim 9 , wherein the at least one block includes a plurality of sample blocks and the controller is further configured, for each of the plurality of sample blocks, to:

instruct the memory apparatus to determine the transistor threshold voltage of the drain-side select gate transistors of one of the plurality of sample blocks;

instruct the memory apparatus to perform the predetermined quantity of erase operations on the one of the plurality of sample blocks of the die of the memory cells;

instruct the memory apparatus to read the drain-side select gate transistors of the one of the plurality of sample blocks using the at least one predetermined transistor threshold voltage and count at least one actual quantity of the drain-side select gate transistors of the one of the plurality of sample blocks having the transistor threshold voltage above the at least one predetermined transistor threshold voltage;

determine whether the at least one actual quantity of the drain-side select gate transistors of the one of the plurality of sample blocks having the transistor threshold voltage above the at least one predetermined transistor threshold voltage exceeds the at least one predetermined failure quantity;

return to determining the transistor threshold voltage of the drain-side select gate transistors of the one of the plurality of sample blocks for a next one of the plurality of sample blocks in response to determining the at least one actual quantity of the drain-side select gate transistors of the one of the plurality of sample blocks having the transistor threshold voltage above the at least one predetermined transistor threshold voltage does not exceed the at least one predetermined failure quantity; and

report the die as failing in response to determining the at least one actual quantity of the drain-side select gate transistors of the one of the plurality of sample blocks having the transistor threshold voltage above the at least one predetermined transistor threshold voltage exceeds the at least one predetermined failure quantity.

12 . The controller as set forth in claim 8 , wherein the memory cells are each connected to one of a plurality of word lines and the controller is further configured, immediately before each of the predetermined quantity of erase operations, to instruct the memory apparatus to apply a pre-program pulse of a pre-program voltage to all of the plurality of word lines of the at least one block being erased, the pre-program voltage selected to shift the memory cells of the at least one block being erased towards a uniform threshold voltage distribution.

13 . The controller as set forth in claim 8 , wherein the die has a three dimensional quadrilateral shape and defines eight corners, the at least one block includes a plurality of sample blocks each disposed at one or more of the eight corners of the die.

14 . A method of operating a memory apparatus including drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage, the method comprising the steps of:

performing a predetermined quantity of erase operations on the memory cells of at least one block of a die of the memory cells; and

reporting the die as failing in response to determining the transistor threshold voltage of one or more of the drain-side select gate transistors of the at least one block does not meet a predetermined criteria.

15 . The method as set forth in claim 14 , wherein the predetermined criteria is at least one predetermined failure quantity the drain-side select gate transistors of the at least one block having the transistor threshold voltage above at least one predetermined transistor threshold voltage.

16 . The method as set forth in claim 15 , wherein the at least one predetermined transistor threshold voltage includes a first predetermined transistor threshold voltage and a second predetermined transistor threshold voltage, the at least one predetermined failure quantity includes a first predetermined failure quantity and a second predetermined failure quantity, and the method further includes the steps of:

reading the drain-side select gate transistors of the at least one block using the first predetermined transistor threshold voltage and counting a first actual quantity of the drain-side select gate transistors of the at least one block having the transistor threshold voltage above the first predetermined transistor threshold voltage;

reading the drain-side select gate transistors of the at least one block using the second predetermined transistor threshold voltage and counting a second actual quantity of the drain-side select gate transistors of the at least one block having the transistor threshold voltage above the first predetermined transistor threshold voltage; and

reporting the die as failing in response to determining at least one of the first actual quantity of the drain-side select gate transistors of the at least one block having the transistor threshold voltage above the first predetermined transistor threshold voltage exceeds at least one of the first predetermined failure quantity and the second predetermined failure quantity or the second actual quantity of the drain-side select gate transistors of the at least one block having the transistor threshold voltage above the second predetermined transistor threshold voltage exceeds the second predetermined failure quantity.

17 . The method as set forth in claim 15 , wherein the at least one block includes a plurality of sample blocks and the method further includes the steps of, for each of the plurality of sample blocks:

determining the transistor threshold voltage of the drain-side select gate transistors of one of the plurality of sample blocks;

performing the predetermined quantity of erase operations on the one of the plurality of sample blocks of the die of the memory cells;

reading the drain-side select gate transistors of the one of the plurality of sample blocks using the at least one predetermined transistor threshold voltage and count at least one actual quantity of the drain-side select gate transistors of the one of the plurality of sample blocks having the transistor threshold voltage above the at least one predetermined transistor threshold voltage;

determining whether the at least one actual quantity of the drain-side select gate transistors of the one of the plurality of sample blocks having the transistor threshold voltage above the at least one predetermined transistor threshold voltage exceeds the at least one predetermined failure quantity;

returning to determining the transistor threshold voltage of the drain-side select gate transistors of the one of the plurality of sample blocks for a next one of the plurality of sample blocks in response to determining the at least one actual quantity of the drain-side select gate transistors of the one of the plurality of sample blocks having the transistor threshold voltage above the at least one predetermined transistor threshold voltage does not exceed the at least one predetermined failure quantity; and

reporting the die as failing in response to determining the at least one actual quantity of the drain-side select gate transistors of the one of the plurality of sample blocks having the transistor threshold voltage above the at least one predetermined transistor threshold voltage exceeds the at least one predetermined failure quantity.

18 . The method as set forth in claim 14 , wherein the memory cells are each connected to one of a plurality of word lines and the method further includes the step of, immediately before each of the predetermined quantity of erase operations, applying a pre-program pulse of a pre-program voltage to all of the plurality of word lines of the at least one block being erased, the pre-program voltage selected to shift the memory cells of the at least one block being erased towards a uniform threshold voltage distribution.

19 . The method as set forth in claim 14 , wherein the die has a three dimensional quadrilateral shape and defines eight corners, the at least one block includes a plurality of sample blocks each disposed at one or more of the eight corners of the die.

20 . The method as set forth in claim 14 , wherein the predetermined quantity of erase operations is approximately 20000 erase operations.