Apparatus and methods for hole current program verify operations
An apparatus is provided that includes a NAND string including a first memory cell coupled to a first word line, and a control circuit coupled to the NAND string. The control circuit is configured to apply a verify voltage to the first word line, perform a verify test on the first memory cell to sense a hole conduction current, and perform a program operation on the first memory cell without performing a pre-charge operation.
1 . An apparatus comprising:
a NAND string comprising a first memory cell coupled to a first word line; and
a control circuit coupled to the NAND string, the control circuit configured to:
apply a verify voltage to the first word line;
perform a verify test on the first memory cell to sense a hole conduction current; and
perform a program operation on the first memory cell without performing a pre-charge operation,
wherein the NAND string comprises a second memory cell coupled to a second word line;
the verify voltage comprises a positive voltage; and
the control circuit is further configured to apply a negative voltage to the second word line during the verify test.
2 . The apparatus of claim 1 , wherein:
the NAND string comprises a channel; and
the control circuit is further configured to cause mobile holes to accumulate in the channel prior to performing the verify test.
3 . The apparatus of claim 1 , wherein:
the NAND string comprises a second memory cell coupled to a second word line; and
the control circuit is further configured to apply a negative voltage to the second word line prior to performing the verify test.
4 . The apparatus of claim 3 , wherein:
the first memory cell and second memory cell comprise a channel; and
the negative voltage applied to the second word line causes mobile holes to accumulate in the channel.
5 . The apparatus of claim 1 , wherein the control circuit is further configured to:
determine that the sensed hole conduction current is above a reference value; and
determine that the first memory cell did not pass the verify test.
6 . The apparatus of claim 1 , wherein the control circuit is further configured to:
determine that the sensed hole conduction current is not above a reference value; and
determine that the first memory cell passed the verify test.
7 . The apparatus of claim 1 , wherein the NAND string comprises a plurality of sub-blocks of memory cells.
8 . The apparatus of claim 1 , wherein the NAND string comprises a string sub-block of a block of memory cells.
9 . The apparatus of claim 1 , wherein the NAND string comprises a plurality of sub-block tiers.