SLC SUB-BLOCK MODE FOR NONVOLATILE MEMORY DEVICES
The memory device includes a memory block with an array of memory cells that are arranged in word lines that are divided into sub-blocks, each of which is associated with an individual read usage threshold. Control circuitry is configured to program the memory cells of the word lines to include data and to perform a plurality of read operations on the word lines of the plurality of sub-blocks and compare a read usage metric associated with a selected sub-block of the plurality of sub-blocks to the read usage threshold that is associated with the selected sub-block. In response to the read usage metric exceeding the read usage threshold, the control circuitry is configured to perform a read refresh operation on the selected sub-block. The individual read usage thresholds associated with the sub-blocks are based on vulnerabilities of the memory cells in the sub-blocks to read disturb.
1 . A method of operating a memory device, comprising the steps of:
preparing a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the plurality of word lines being divided into a plurality of sub-blocks, and wherein each of the sub-blocks is associated with an individual read usage threshold;
programming the memory cells of the word lines to include data;
performing a plurality of read operations on the word lines of the plurality of sub-blocks;
comparing a read usage metric associated with a selected sub-block of the plurality of sub-blocks to the read usage threshold that is associated with the selected sub-block;
in response to the read usage metric exceeding the read usage threshold, performing a read refresh operation on the selected sub-block; and
wherein the individual read usage thresholds associated with the sub-blocks are based on vulnerabilities of the memory cells in the sub-blocks to read disturb.
2 . The method as set forth in claim 1 , wherein the read usage metric is a read cycle counter and wherein the read usage threshold is a predetermined maximum read cycle count.
3 . The method as set forth in claim 1 , wherein the plurality of sub-blocks includes four sub-blocks.
4 . The method as set forth in claim 3 , wherein two of the four sub-blocks have high vulnerability to read disturb and are associated with a first read usage threshold and wherein the other two of the four sub-blocks have low vulnerability to read disturb and are associated with a second read usage threshold, and wherein the second read usage threshold is greater than the first read usage threshold.
5 . The method as set forth in claim 1 , wherein at least one of the plurality of sub-blocks includes a different number of word lines than at least one of the other sub-blocks of the plurality of sub-blocks.
6 . The method as set forth in claim 1 , wherein the memory block is a first memory block and wherein the memory device includes a plurality of memory blocks that have identical sub-block arrangements; and
wherein the read refresh operation is a relocation operation where the data contained in the memory cells of the selected sub-block is relocated to a sub-block of a different memory block in the memory device.
7 . A memory device, comprising:
a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the plurality of word lines being divided into a plurality of sub-blocks, and wherein each of the sub-blocks is associated with an individual read usage threshold;
control circuitry that is configured to;
program the memory cells of the word lines to include data,
perform a plurality of read operations on the word lines of the plurality of sub-blocks,
compare a read usage metric associated with a selected sub-block of the plurality of sub-blocks to the read usage threshold that is associated with the selected sub-block,
in response to the read usage metric exceeding the read usage threshold, perform a read refresh operation on the selected sub-block; and
wherein the individual read usage thresholds associated with the sub-blocks are based on vulnerabilities of the memory cells in the sub-blocks to read disturb.
8 . The memory device as set forth in claim 7 , wherein the read usage metric is a read cycle counter and wherein the read usage threshold is a predetermined maximum read cycle count.
9 . The memory device as set forth in claim 7 , wherein the plurality of sub-blocks includes four sub-blocks.
10 . The memory device as set forth in claim 9 , wherein two of the four sub-blocks have high vulnerability to read disturb and are associated with a first read usage threshold and wherein the other two of the four sub-blocks have low vulnerability to read disturb and are associated with a second read usage threshold, and wherein the second read usage threshold is greater than the first read usage threshold.
11 . The memory device as set forth in claim 7 , wherein at least one of the plurality of sub-blocks includes a different number of word lines than at least one of the other sub-blocks of the plurality of sub-blocks.
12 . The memory device as set forth in claim 7 , wherein the memory block is a first memory block and wherein the memory device includes a plurality of memory blocks that have identical sub-block arrangements; and
wherein the read refresh operation is a relocation operation where the data contained in the memory cells of the selected sub-block is relocated by the control circuitry to a sub-block of a different memory block in the memory device.
13 . A computing system, comprising:
a processing unit;
a plurality of high bandwidth flash packages, each of the high bandwidth flash packages including a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the plurality of word lines being divided into a plurality of sub-blocks, and wherein each of the sub-blocks is associated with an individual read usage threshold;
control circuitry that is configured to;
program the memory cells of the word lines to include data,
perform a plurality of read operations on the word lines of the plurality of sub-blocks,
compare a read usage metric associated with a selected sub-block of the plurality of sub-blocks to the read usage threshold that is associated with the selected sub-block,
in response to the read usage metric exceeding the read usage threshold, perform a read refresh operation on the selected sub-block; and
wherein the individual read usage thresholds associated with the sub-blocks are based on vulnerabilities of the memory cells in the sub-blocks to read disturb.
14 . The computing system as set forth in claim 13 , wherein the read usage metric is a read cycle counter and wherein the read usage threshold is a predetermined maximum read cycle count.
15 . The computing system as set forth in claim 13 , wherein the plurality of sub-blocks includes four sub-blocks.
16 . The computing system as set forth in claim 15 , wherein two of the four sub-blocks have high vulnerability to read disturb and are associated with a first read usage threshold and wherein the other two of the four sub-blocks have low vulnerability to read disturb and are associated with a second read usage threshold, and wherein the second read usage threshold is greater than the first read usage threshold.
17 . The computing system as set forth in claim 13 , wherein at least one of the plurality of sub-blocks includes a different number of word lines than at least one of the other sub-blocks of the plurality of sub-blocks.
18 . The computing system as set forth in claim 13 , wherein the memory block is a first memory block and wherein each of the high bandwidth flash package includes a plurality of memory blocks that have identical sub-block arrangements; and
wherein the read refresh operation is a relocation operation where the data contained in the memory cells of the selected sub-block is relocated by the control circuitry to a sub-block of a different memory block in the memory device.
19 . The computing system as set forth in claim 13 , wherein the plurality of high bandwidth flash packages includes at least five high bandwidth flash packages that are in communication with a single processor unit.
20 . The computing system as set forth in claim 13 , wherein the data includes large language model weight matrices.