In-place refresh techniques for non-volatile memory devices
The memory device includes a memory block that includes an array of memory cells that are arranged in a plurality of word lines. The memory device also includes circuitry for programming the memory cells of the memory block. The circuitry is configured to program the memory cells of the memory block to a single bit per memory cell storage format that includes a first data state and a second data state that is at a higher threshold voltage range than the first data state. In response to the memory cells experiencing data retention stress that causes the memory cells in the second data state to fall, the circuitry is configured to perform an in-place programming operation on a selected word line of the plurality of word lines. The in-place programming operation includes the circuitry programming the memory cells in the second data state to higher threshold voltages.
1 . A method of operating a memory device, comprising the steps of:
preparing a memory block that includes an array of memory cells that are arranged in a plurality of word lines;
programming the memory cells of the memory block to a single bit per memory cell storage format that includes a first data state and a second data state that is at a higher threshold voltage range than the first data state; and
in response to the memory cells experiencing data retention stress that causes the memory cells in the second data state to fall, performing an in-place programming operation on a selected word line of the plurality of word lines, the in-place programming operation including programming the memory cells in the second data state to higher threshold voltages.
2 . The method as set forth in claim 1 , wherein the step of programming the memory cells of the memory block includes a verify operation with a verify voltage and wherein the step of performing the in-place programming operation on the selected word line includes a verify operation with the verify voltage.
3 . The method as set forth in claim 1 , wherein prior to the step of performing the in-place programming operation on the selected word line, all of the memory cells in the memory block have threshold voltages that are no greater than 2 V.
4 . The method as set forth in claim 3 , wherein prior to the step of performing the in-place programming operation, all of the memory cells in the memory block have threshold voltages that are greater than approximately −1.5 V.
5 . The method as set forth in claim 1 , further including the step of determining if substantial data retention stress has occurred in the memory cells prior to the step of performing the in-place programming operation.
6 . The method as set forth in claim 5 , wherein during the step of programming the memory cells of the memory block, the memory cells of the memory block are programmed from an erased condition to the first data state and to the second data state.
7 . The method as set forth in claim 1 , wherein during the in-place programming operation, between program loops, a programming voltage is increased by a step size that is no greater than approximately 0.2 V.
8 . A memory device, comprising:
a memory block that includes an array of memory cells that are arranged in a plurality of word lines; and
circuitry for programming the memory cells of the memory block and being configured to;
program the memory cells of the memory block to a single bit per memory cell storage format that includes a first data state and a second data state that is at a higher threshold voltage range than the first data state;
in response to the memory cells experiencing data retention stress that causes the memory cells in the second data state to fall, perform an in-place programming operation on a selected word line of the plurality of word lines, the in-place programming operation including the circuitry programming the memory cells in the second data state to higher threshold voltages.
9 . The memory device as set forth in claim 8 , wherein when programming the memory cells of the memory block, the circuitry performs a verify operation that includes a verify voltage and when performing the in-place programming operation, the circuitry performs a verify operation that includes the verify voltage.
10 . The memory device as set forth in claim 8 , wherein prior to the circuitry performing the in-place programming operation, all of the memory cells in the memory block have threshold voltages that are no greater than 2 V.
11 . The memory device as set forth in claim 10 , wherein prior to performing the in-place programming operation, all of the memory cells in the memory block have threshold voltages that are greater than approximately −1.5 V.
12 . The memory device as set forth in claim 8 , wherein the circuitry is further configured to determine if substantial data retention stress has occurred in the memory cells prior to performing the in-place programming operation.
13 . The memory device as set forth in claim 11 , wherein when programming the memory cells of the memory block, the circuitry programs the memory block from an erased condition to the first data state and the second data state.
14 . The memory device as set forth in claim 8 , wherein during the in-place programming operation, between program loops, the circuitry increases a programming voltage by a step size that is no greater than approximately 0.2 V.
15 . A computing system, comprising:
a processor unit;
a plurality of non-volatile memory packages in electrical communication with the processor unit, at least one of the non-volatile memory packages including a memory block that includes an array of memory cells that are arranged in a plurality of word lines; and
the at least one non-volatile memory package further including circuitry for performing an in-place refresh operation and being configured to;
program the memory cells of the memory block to a single bit per memory cell storage format that includes a first data state and a second data state that is at a higher threshold voltage range than the first data state;
in response to the memory cells experiencing data retention stress that causes the memory cells in the second data state to fall, perform the in-place refresh operation on a selected word line of the plurality of word lines, the in-place refresh operation including the circuitry programming the memory cells in the second data state to higher threshold voltages.
16 . The computing system as set forth in claim 15 , wherein when programming the memory cells of the memory block, the circuitry performs verify operations using a verify voltage and during the in-place refresh operation, the circuitry performs verify operations using the verify voltage.
17 . The computing system as set forth in claim 15 , wherein prior to the circuitry performing the in-place refresh operation, all of the memory cells in the memory block have threshold voltages that are no greater than 2 V.
18 . The computing system as set forth in claim 17 , wherein prior to performing the in-place refresh operation, all of the memory cells in the memory block have threshold voltages that are greater than approximately −1.5 V.
19 . The computing system as set forth in claim 15 , wherein the circuitry is further configured to determine if substantial data retention stress has occurred in the memory cells prior to performing the in-place refresh operation.
20 . The computing system as set forth in claim 19 , wherein when programming the memory cells of the memory block, the circuitry programs the memory block from an erased condition to the first data state and the second data state.