DISCHARGE-FREE READ OPERATIONS FOR HIGH BANDWIDTH NONVOLATILE MEMORY DEVICES
The memory device includes a memory block with a plurality of strings with non-volatile memory cells, each of which is coupled to one of a plurality of word lines. The memory device also includes control circuitry that is coupled to the memory array. The control circuitry is configured to perform a first read operation on a first non-volatile memory cell in the memory block while a plurality of unselected word lines of the plurality of word lines are biased to a read pass voltage. The control circuitry is also configured to perform a second read operation on a second non-volatile memory cell in the memory block while the plurality of unselected word lines are biased to the read pass voltage. The unselected word lines are not discharged and remain biased to the read pass voltage during and between the first read operation and the second read operation.
1 . A memory device, comprising:
a memory block including a plurality of strings, each string comprising a plurality of non-volatile memory cells, each non-volatile memory cell being coupled to one of a plurality of word lines;
control circuitry coupled to the memory array, the control circuitry being configured to;
perform a first read operation on a first non-volatile memory cell in the memory block while a plurality of unselected word lines of the plurality of word lines are biased to a read pass voltage, and
perform a second read operation on a second non-volatile memory cell in the memory block while the plurality of unselected word lines are biased to the read pass voltage; and
wherein the unselected word lines are not discharged and remain biased to the read pass voltage during and between the first read operation and the second read operation.
2 . The memory device as set forth in claim 1 , wherein the first non-volatile memory cell is in the same word line as the second non-volatile memory cell and is in a different string than the second non-volatile memory cell.
3 . The memory device as set forth in claim 1 , wherein the first non-volatile memory cell is in the same string as the second non-volatile memory cells and is in a different word line from the second non-volatile memory cell.
4 . The memory device as set forth in claim 1 , wherein the first non-volatile memory cell is in a different word line than and is in a different string than the second non-volatile memory cell.
5 . The memory device as set forth in claim 1 , wherein the first and second memory cells are programmed to one bit of data per memory cell.
6 . The memory device as set forth in claim 1 , wherein during the first read operation, the control circuitry discharges a current through the first non-volatile memory cell, and wherein during the second read operation, the control circuitry discharges a current through the second non-volatile memory cell.
7 . A method of operating a memory device, comprising the steps of:
preparing a memory block that includes a plurality of strings, each string comprising a plurality of non-volatile memory cells, each non-volatile memory cell being coupled to one of a plurality of word lines;
performing a first read operation on a first non-volatile memory cell in the memory block while a plurality of unselected word lines of the plurality of word lines are biased to a read pass voltage;
performing a second read operation on a second non-volatile memory cell in the memory block while the plurality of unselected word lines are biased to the read pass voltage; and
wherein the unselected word lines are not discharged and remain biased to the read pass voltage during and between the first read operation and the second read operation.
8 . The method as set forth in claim 7 , wherein the first non-volatile memory cell is in the same word line as the second non-volatile memory cell and is in a different string than the second non-volatile memory cell.
9 . The method as set forth in claim 7 , wherein the first non-volatile memory cell is in the same string as the second non-volatile memory cells and is in a different word line from the second non-volatile memory cell.
10 . The method as set forth in claim 7 , wherein the first non-volatile memory cell is in a different word line than and is in a different string than the second non-volatile memory cell.
11 . The method as set forth in claim 7 , wherein the first and second memory cells are programmed to one bit of data per memory cell.
12 . The method as set forth in claim 7 , wherein during the first read operation, the control circuitry discharges a current through the first non-volatile memory cell, and wherein during the second read operation, the control circuitry discharges a current through the second non-volatile memory cell.
13 . A computing system, comprising:
a processing unit;
a plurality of high bandwidth flash packages in electrical communication with the processing unit, at least one of the high bandwidth flash packages including a memory block with a plurality of strings, each string comprising a plurality of non-volatile memory cells, each non-volatile memory cell being coupled to one of a plurality of word lines;
control circuitry coupled to the memory array, the control circuitry being configured to;
perform a first read operation on a first non-volatile memory cell in the memory block while a plurality of unselected word lines of the plurality of word lines are biased to a read pass voltage, and
perform a second read operation on a second non-volatile memory cell in the memory block while the plurality of unselected word lines are biased to the read pass voltage; and
wherein the unselected word lines are not discharged and remain biased to the read pass voltage during and between the first read operation and the second read operation.
14 . The computing system as set forth in claim 13 , wherein the first non-volatile memory cell is in the same word line as the second non-volatile memory cell and is in a different string than the second non-volatile memory cell.
15 . The computing system as set forth in claim 13 , wherein the first non-volatile memory cell is in the same string as the second non-volatile memory cells and is in a different word line from the second non-volatile memory cell.
16 . The computing system as set forth in claim 13 , wherein the first non-volatile memory cell is in a different word line than and is in a different string than the second non-volatile memory cell.
17 . The computing system as set forth in claim 13 , wherein the first and second memory cells are programmed to one bit of data per memory cell.
18 . The computing system as set forth in claim 13 , wherein during the first read operation, the control circuitry discharges a current through the first non-volatile memory cell, and wherein during the second read operation, the control circuitry discharges a current through the second non-volatile memory cell.
19 . The computing system as set forth in claim 13 , wherein the first and second read operations are large language model operations.
20 . The computing system as set forth in claim 13 , wherein the plurality of high bandwidth flash packages are able to communicate with the processing unit during read operations at a bandwidth of at least 3 TB/s.