Granted Patent B2

US 12,602,164 · App. 18/676,911 · Granted Apr 14, 2026

Inventors: Roshini Hegde (Bangalore, IN); Ramanathan Muthiah (Bangalore, IN)

Assignee: Sandisk Technologies, Inc.

G06F3/0613G06F3/0653G06F3/0659G06F3/0679

Abstract

Claims (55)

1 . A data storage device comprising:

a memory comprising a plurality of memory dies, wherein the plurality of memory dies comprises a plurality of subsets of memory dies in sequential physical locations; and

one or more processors, individually or in combination, configured to:

determine that first and second commands are in a queue, wherein executing the first command uses relatively-more involvement of the one or more processors and relatively-less involvement of the memory, and wherein executing the second command uses relatively-more involvement of the memory and relatively-less involvement of the one or more processors;

determine whether a first temperature of the memory and/or a second temperature of the one or more processors is above a threshold temperature;

in response to determining that only the first temperature of the memory is above the threshold temperature:

retrieve the first command, but not the second command, from the queue;

execute the first command; and

retrieve the second command from the queue only after the first temperature of the memory is no longer above the threshold temperature; and

in response to determining that only the second temperature of the one or more processors is above the threshold temperature:

retrieve the second command, but not the first command, and at least one additional command that uses relatively-more involvement of the memory and relatively-less involvement of the one or more processors from the queue;

execute the second command and the at least one additional command in a sequence such that some, but not all, memory dies in each subset are operational, and wherein the memory dies that are operational are within a temperature limit; and

retrieve the first command from the queue only after the second temperature of the one or more processors is no longer above the threshold temperature.

2 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to perform full-device throttling in response to both the first temperature of the memory and the second temperature of the one or more processors being above the threshold temperature.

3 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to perform a third command without throttling in response to a size of the third command being below a threshold.

4 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to use a thermal credit point system to manage thermal throttling.

5 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to use a feedback loop to determine a temperature delta when a command selection policy changes and impacts an overall temperature curve of the data storage device.

6 . The data storage device of claim 1 , wherein the one or more processors are part of a controller, and the one or more processors, individually or in combination, are further configured to reduce a third temperature of the controller by disabling one or more hardware components of the controller.

7 . The data storage device of claim 6 , wherein the one or more hardware components of the controller comprise: a hardware-aggregate write accumulator, a global access table search engine, a dedicated controller to interact with a host memory buffer/controller, and a hardware accelerator.

8 . The data storage device of claim 1 , wherein the one or more processors are part of a controller, and the one or more processors, individually or in combination, are further configured to reduce a third temperature of the controller by performing at least one of the following: reducing load on the controller by limiting a depth of the queue, reducing a frequency of the controller, modifying a flash interface module (FIM) toggle mode of the controller, or performing a memory trim.

9 . The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to determine a most-impacted memory die and select commands that reduce a workload on the most-impacted memory die.

10 . The data storage device of claim 1 , wherein the command whose execution uses relatively-more involvement of the memory and relatively-less involvement of the one or more processors comprises a sequential command.

11 . The data storage device of claim 1 , wherein the data storage device comprises a solid-state drive.

12 . The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.

13 . A method comprising:

performing in a data storage device comprising a memory and a controller, wherein the memory comprising a plurality of memory dies and wherein the plurality of memory dies comprises a plurality of subsets of memory dies in sequential physical locations:

determining that first and second commands are in a submission queue, wherein executing the first command uses relatively-more involvement of the controller and relatively-less involvement of the memory, and wherein executing the second command uses relatively-more involvement of the memory and relatively-less involvement of the controller;

determining that one, but not both, of a first temperature the memory and a second temperature of the controller is above a thermal throttling threshold temperature;

in response to determining that only the first temperature of the memory is above the thermal throttling threshold temperature:

retrieving the first command, but not the second command, from the submission queue;

executing the first command; and

retrieving the second command from the submission queue only after the first temperature of the memory is no longer above the thermal throttling threshold temperature; and

in response to determining that only the second temperature of the controller is above the thermal throttling threshold temperature:

retrieving the second command, but not the first command, and at least one additional command that uses relatively-more involvement of the memory and relatively-less involvement of the controller from the submission queue;

executing the second command and the at least one additional command in a sequence such that some, but not all, memory dies in each subset are operational, and wherein the memory dies that are operational are within a temperature limit; and

retrieving the first command from the submission queue only after the second temperature of the controller is no longer above the thermal throttling threshold temperature.

14 . The method of claim 13 , further comprising using a thermal credit point system to manage thermal throttling.

15 . The method of claim 13 , further comprising reducing the second temperature of the controller by disabling one or more hardware components of the controller.

16 . The method of claim 15 , wherein the one or more hardware components of the controller comprise: a hardware-aggregate write accumulator, a global access table search engine, a dedicated controller to interact with a host memory buffer/controller, and a hardware accelerator.

17 . The method of claim 13 , further comprising reducing the second temperature of the controller by performing at least one of the following: reducing load on the controller by limiting a depth of the submission queue, reducing a frequency of the controller, modifying a flash interface module (FIM) toggle mode of the controller, or performing a memory trim.

18 . The method of claim 13 , further comprising using temperature sensors to determine the first temperature of the memory and the second temperature of the controller.

19 . A data storage device comprising:

a memory comprising a plurality of memory dies wherein the plurality of memory dies comprises a plurality of subsets of memory dies in sequential physical locations;

one or more processors; and

means for:

determining that first and second commands are in a queue, wherein executing the first command uses relatively-more involvement of the one or more processors and relatively-less involvement of the memory, and wherein executing the second command uses relatively-more involvement of the memory and relatively-less involvement of the one or more processors;

determining whether a first temperature of the memory and/or a second temperature of the one or more processors is above a threshold temperature;

in response to determining that only the first temperature of the memory is above the threshold temperature:

retrieving the first command, but not the second command, from the queue;

executing the first command; and

retrieving the second command from the queue only after the first temperature of the memory is no longer above the threshold temperature; and

in response to determining that only the second temperature of the one or more processors is above the threshold temperature:

retrieving the second command, but not the first command, and at least one additional command that uses relatively-more involvement of the memory and relatively-less involvement of the one or more processors from the queue;

executing the second command and the at least one additional command in a sequence such that some, but not all, memory dies in each subset are operational, and wherein the memory dies that are operational are within a temperature limit; and

retrieving the first command from the queue only after the second temperature of the one or more processors is no longer above the threshold temperature.

Assignments (4)

Continuity (1)

References Cited (17)