Large array of upward pointing p-i-n diodes having large and uniform current
A monolithic three-dimensional memory array is provided that includes a first memory level and a second memory level disposed above or below the first memory level. The first memory level includes a plurality of vertically oriented p-i-n diodes that each include a bottom heavily doped p type region. The second memory level includes a plurality of vertically oriented p-i-n diodes that each include a bottom heavily doped n type region. Numerous other aspects are also provided.
1. A monolithic three-dimensional memory array comprising:
a first memory level comprising a plurality of vertically oriented p-i-n diodes that each comprise a bottom heavily doped p-type region; and
a second memory level comprising a plurality of vertically oriented p-i-n diodes that each comprise a bottom heavily doped n-type region, the second memory level disposed above or below the first memory level,
wherein read currents of the p-i-n diodes of the first memory level are within an order of magnitude of one another.
2. The monolithic three-dimensional memory array of claim 1 , wherein when a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode of the first memory level, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes of the first memory level.
3. The monolithic three-dimensional memory array of claim 1 , wherein when a voltage between about 1.8 volts and about 2.2 volts is applied across each p-i-n diode of the first memory level, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes of the first memory level.
4. The monolithic three-dimensional memory array of claim 1 , further comprising a plurality of resistivity-switching elements, each p-i-n diode coupled to a corresponding one of the resistivity-switching elements.
5. The monolithic three-dimensional memory array of claim 4 , wherein each resistivity-switching element comprises one or more of Ni x O y , Nb x O y , Ti x O y , Hf x O y , Al x O y , Mg x O y , Co x O y , Cr x O y , V x O y , Zn x O y , Zr x O y , B x N y and Al x N y .
6. The monolithic three-dimensional memory array of claim 1 , wherein each p-i-n diode is in contact with a silicide, germanide, or silicide-germanide layer.
7. A monolithic three-dimensional circuit comprising:
a first circuit level comprising a plurality of vertically oriented p-i-n diodes, wherein each p-i-n diode of the first circuit level comprises a bottom heavily doped p-type region; and
a second circuit level comprising a plurality of vertically oriented p-i-n diodes, wherein each p-i-n diode of the second circuit level comprises a bottom heavily doped n-type region,
wherein the second circuit level is monolithically formed above the first circuit level, and
wherein read currents of the p-i-n diodes of the first circuit level are within an order of magnitude of one another.
8. The monolithic three-dimensional circuit of claim 7 , wherein when a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode of the first circuit level, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes of the first circuit level.
9. The monolithic three-dimensional circuit of claim 7 , wherein when a voltage between about 1.8 volts and about 2.2 volts is applied across each p-i-n diode of the first circuit level, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes of the first circuit level.
10. The monolithic three-dimensional circuit of claim 7 , further comprising a plurality of resistivity-switching elements, each p-i-n diode coupled to a corresponding one of the resistivity-switching elements.
11. The monolithic three-dimensional circuit of claim 10 , wherein each resistivity-switching element comprises one or more of Ni x O y , Nb x O y , Ti x O y , Hf x O y , Al x O y , MgO x O y , Co x O y , Cr x O y , V x O y , Zn x O y , Zr x O y , B x N y and Al x N y .
12. The monolithic three-dimensional circuit of claim 7 , wherein each p-i-n diode is in contact with a silicide, germanide, or silicide-germanide layer.
13. A method comprising:
forming a first memory level comprising a plurality of vertically oriented p-i-n diodes that each comprise a bottom heavily doped p-type region;
forming a second memory level comprising a plurality of vertically oriented p-i-n diodes that each comprise a bottom heavily doped n-type region, the second memory level disposed above or below the first memory level;
applying read voltages across the p-i-n diodes of the first memory level; and
measuring corresponding read currents through the p-i-n diodes of the first memory level,
wherein the measured read currents are within an order of magnitude of one another.
14. The method of claim 13 , further comprising forming a plurality of resistivity-switching elements, each p-i-n diode coupled to a corresponding one of the resistivity-switching elements.
15. The method of claim 14 , wherein each resistivity-switching element comprises one or more of Ni x O y , Nb x O y , Ti x O y , Hf x O y , Al x O y , Mg x O y , Co x O y , Cr x O y , V x O y , Zn x O y , Zr x O y , B x N y and Al x N y .
16. The method of claim 13 , further comprising forming each p-i-n diode in contact with a silicide, germanide, or silicide-germanide layer.