Patent Assignment
Reel/Frame 038807/0948
CHANGE OF NAME
Recorded: 2016-05-25
Received: 2016-05-25
Pages: 17
Assignor
SANDISK TECHNOLOGIES INC
Executed: 2016-05-16
Assignee
SANDISK TECHNOLOGIES LLC
6900 DALLAS PARKWAY, SUITE 325, PLANO, TX, 75024, UNITED STATES
Covered Applications
(100)
I/O PIN CAPACITANCE REDUCTION USING TSVS
App. No. 14/969,381
→
TIMED MULTIPLEX SENSING
App. No. 14/887,547
→
3D NAND Memory with Socketed Floating Gate Cells and Process Therefor
App. No. 14/825,405
→
SYSTEM AND METHOD FOR DISTRIBUTED COMPUTING IN NON-VOLATILE MEMORY
App. No. 14/815,093
→
Balancing Programming Speeds Of Memory Cells In A 3D Stacked Memory
App. No. 14/750,250
→
THREE-DIMENSIONAL MEMORY DEVICES CONTAINING MEMORY STACK STRUCTURES WITH POSITION-INDEPENDENT THRESHOLD VOLTAGE
App. No. 14/746,042
→
DEVICE FOR ESTIMATING PLAYBACK TIME AND HANDLING A CUMULATIVE PLAYBACK TIME PERMISSION
App. No. 14/728,700
→
Reducing Hot Electron Injection Type Of Read Disturb In 3D Non-Volatile Memory
App. No. 14/728,615
→
NON-VOLATILE STORAGE SYSTEM BIASING CONDITIONS FOR STANDBY AND FIRST READ
App. No. 14/700,134
→
DATA STORAGE DEVICE AND METHOD TO CORRECT BIT VALUES USING MULTIPLE READ VOLTAGES
App. No. 14/698,626
→
PARITY SCHEME FOR A DATA STORAGE DEVICE
App. No. 14/694,825
→
METHODS TO IMPROVE PROGRAMMING OF SLOW CELLS
App. No. 14/681,653
→
PARTIAL BLOCK ERASE FOR A THREE DIMENSIONAL (3D) MEMORY
App. No. 14/676,670
→
Temperature Dependent Voltage To Unselected Drain Side Select Transistor During Program Of 3D NAND
App. No. 14/673,265
→
SYSTEM AND METHOD FOR DISTRIBUTED COMPUTING IN NON-VOLATILE MEMORY
App. No. 14/671,336
→
METHOD OF REDUCING HOT ELECTRON INJECTION TYPE OF READ DISTURB IN DUMMY MEMORY CELLS
App. No. 14/669,247
→
Digitally Controlled Source Side Select Gate Offset in 3D NAND Memory Erase
App. No. 14/667,014
→
MULTI-LEVEL CONTACT TO A 3D MEMORY ARRAY AND METHOD OF MAKING
App. No. 14/631,047
→
Erase Operation For 3D Non-Volatile Memory With Controllable Gate-Induced Drain Leakage Current
App. No. 14/631,080
→
FAST-READING NAND FLASH MEMORY
App. No. 14/631,027
→
THREE-DIMENSIONAL MEMORY DEVICE WITH STRESS COMPENSATION LAYER WITHIN A WORD LINE STACK
App. No. 14/628,741
→
SYSTEMS AND METHODS FOR PERSISTENT ATOMIC STORAGE OPERATIONS
App. No. 14/627,869
→
Data Recovery In A 3D Memory Device With A Short Circuit Between Word Lines
App. No. 14/627,575
→
COMPENSATING SOURCE SIDE RESISTANCE VERSUS WORD LINE
App. No. 14/625,363
→
PROCESS AND APPARATUS TO REDUCE DECLARED CAPACITY OF A STORAGE DEVICE BY CONDITIONALLY TRIMMING
App. No. 14/621,148
→
3D MEMORY HAVING CRYSTALLINE SILICON NAND STRING CHANNEL
App. No. 14/619,836
→
Erase Verify In Non-Volatile Memory
App. No. 14/619,857
→
Reduced Current Program Verify In Non-Volatile Memory
App. No. 14/619,875
→
Reduced Erase-Verify Voltage For First-Programmed Word Line In A Memory Device
App. No. 14/617,182
→
MULTILEVEL INTERCONNECT STRUCTURE AND METHODS OF MANUFACTURING THE SAME
App. No. 14/614,757
→
Weak Erase Of A Dummy Memory Cell To Counteract Inadvertent Programming
App. No. 14/612,561
→
ADAPTIVE INCREASE IN CONTROL GATE VOLTAGE OF A DUMMY MEMORY CELL TO COMPENSATE FOR INADVERTENT PROGRAMMING
App. No. 14/612,601
→
Voltage Kick to Non-Selected Word Line During Programming
App. No. 14/612,010
→
Word Line Kick During Sensing: Trimming and Adjacent Word Lines
App. No. 14/611,997
→
MULTILEVEL MEMORY STACK STRUCTURE AND METHODS OF MANUFACTURING THE SAME
App. No. 14/611,785
→
LOW PROFILE WIRE BONDED USB DEVICE
App. No. 14/612,115
→
NAND STRING CONTAINING SELF-ALIGNED CONTROL GATE SIDEWALL CLADDING
App. No. 14/607,339
→
Fast Adaptive Trimming of Operating Parameters for Non-Volatile Memory Devices
App. No. 14/600,693
→
ADAPTIVE INITIAL PROGRAM VOLTAGE FOR NON-VOLATILE MEMORY
App. No. 14/600,588
→
Continuous Capacitor Health Monitoring and Power Supply System
App. No. 14/599,128
→
TECHNIQUES FOR DETECTION AND TREATING MEMORY HOLE TO LOCAL INTERCONNECT MARGINALITY DEFECTS
App. No. 14/596,751
→
METHODS AND APPARATUS FOR CLOCK OSCILLATOR TEMPERATURE COEFFICIENT TRIMMING
App. No. 14/596,789
→
ADAPTIVE TARGET CHARGE TO EQUALIZE BIT ERRORS ACROSS PAGE TYPES
App. No. 14/596,174
→
MEMORY SYSTEM AND METHOD FOR IMPROVING READ LATENCY OF A HIGH-PRIORITY PARTITION
App. No. 14/594,934
→
Detecting Programmed Word Lines Based On NAND String Current
App. No. 14/594,473
→
METHOD OF MAKING ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE
App. No. 14/587,368
→
AVERAGE VOLTAGE BAND DETECTION AND USE FOR TUNING OF VOLTAGES IN ASICS
App. No. 14/586,502
→
THREE-DIMENSIONAL MEMORY STRUCTURE HAVING A BACK GATE ELECTRODE
App. No. 14/564,555
→
Pseudo Block Operation Mode In 3D NAND
App. No. 14/563,243
→
Dynamic Bit Line Bias For Programming Non-Volatile Memory
App. No. 14/561,841
→
Power Management for Nonvolatile Memory Array
App. No. 14/558,172
→
OPERATION MODES FOR AN INVERTED NAND ARCHITECTURE
App. No. 14/557,004
→
THREE DIMENSIONAL NAND DEVICE AND METHOD OF CHARGE TRAP LAYER SEPARATION AND FLOATING GATE FORMATION IN THE NAND DEVICE
App. No. 14/546,671
→
Boundary Word Line Operation in Nonvolatile Memory
App. No. 14/546,591
→
3D Non-Volatile Storage With Transistor Decoding Structure
App. No. 14/543,342
→
MEMORY ARRAY HAVING DIVIDED APART BIT LINES AND PARTIALLY DIVIDED BIT LINE SELECTOR SWITCHES
App. No. 14/543,690
→
THREE DIMENSIONAL NAND DEVICE AND METHOD OF MAKING THEREOF
App. No. 14/539,307
→
THREE DIMENSIONAL NAND DEVICE WITH SILICIDE CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF
App. No. 14/539,811
→
METHOD OF MAKING A THREE DIMENSIONAL NAND DEVICE
App. No. 14/539,372
→
DEVICES AND METHODS TO CONDITIONALLY SEND PARAMETER VALUES TO NON-VOLATILE MEMORY
App. No. 14/538,128
→
SELECTIVE WORD LINE ERASE IN 3D NON-VOLATILE MEMORY
App. No. 14/536,923
→
3D Non-Volatile Memory With Metal Silicide Interconnect
App. No. 14/533,576
→
Storage Device and Method for Performing a Self-Refresh Operation
App. No. 14/532,611
→
FLASH MEMORY WITH P-TYPE FLOATING GATE
App. No. 14/531,857
→
HIGH DIELECTRIC CONSTANT ETCH STOP LAYER FOR A MEMORY STRUCTURE
App. No. 14/530,220
→
Systems and Methods for Lower Page Writes
App. No. 14/528,892
→
RIGID WAVE PATTERN DESIGN ON CHIP CARRIER SUBSTRATE AND PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR AND ELECTRONIC SUB-SYSTEM PACKAGING
App. No. 14/528,671
→
Group Word Line Erase And Erase-Verify Methods For 3D Non-Volatile Memory
App. No. 14/524,153
→
NON-VOLATILE STORAGE WITH TEMPERATURE COMPENSATION BASED ON NEIGHBOR STATE INFORMATION
App. No. 14/524,238
→
METHODS FOR REDUCING BODY EFFECT AND INCREASING JUNCTION BREAKDOWN VOLTAGE
App. No. 14/523,848
→
SINGLE-STAGE FOLDED CASCODE BUFFER AMPLIFIERS WITH ANALOG COMPARATORS
App. No. 14/522,678
→
In-Situ Block Folding for Nonvolatile Memory
App. No. 14/520,909
→
BOTTOM RECESS PROCESS FOR AN OUTER BLOCKING DIELECTRIC LAYER INSIDE A MEMORY OPENING
App. No. 14/519,733
→
Weak Erase After Programming To Improve Data Retention In Charge-Trapping Memory
App. No. 14/518,340
→
COMPACT THREE DIMENSIONAL VERTICAL NAND AND METHOD OF MAKING THEREOF
App. No. 14/517,122
→
VERTICAL NAND DEVICE CONTAINING PERIPHERAL DEVICES ON EPITAXIAL SEMICONDUCTOR PEDESTAL
App. No. 14/517,134
→
BIASING OF UNSELECTED BLOCKS OF NON-VOLATILE MEMORY TO REDUCE LOADING
App. No. 14/515,762
→
Vertical TFT With Tunnel Barrier
App. No. 14/515,054
→
Non-Volatile Storage Having Oxide/Nitride Sidewall
App. No. 14/511,834
→
DIRECT MULTI-LEVEL CELL PROGRAMMING
App. No. 14/509,602
→
NON-VOLATILE MEMORY AND METHOD WITH ADJUSTED TIMING FOR INDIVIDUAL PROGRAMMING PULSES
App. No. 14/508,352
→
Programming Of Drain Side Word Line To Reduce Program Disturb And Charge Loss
App. No. 14/508,164
→
NON-VOLATILE MEMORY AND METHOD WITH PEAK CURRENT CONTROL
App. No. 14/507,647
→
COMPENSATION SCHEME FOR NON-VOLATILE MEMORY
App. No. 14/506,607
→
COMPENSATION SCHEME FOR NON-VOLATILE MEMORY
App. No. 14/506,610
→
THREE DIMENSIONAL NAND DEVICE WITH SILICON GERMANIUM HETEROSTRUCTURE CHANNEL
App. No. 14/505,870
→
LATCH INITIALIZATION FOR A DATA STORAGE DEVICE
App. No. 14/504,268
→
THREE DIMENSIONAL MEMORY DEVICE HAVING COMB-SHAPED SOURCE ELECTRODE AND METHODS OF MAKING THEREOF
App. No. 14/501,539
→
APPARATUS AND METHODS FOR SENSING HARD BIT AND SOFT BITS
App. No. 14/500,476
→
MODIFYING PROGRAM PULSES BASED ON INTER-PULSE PERIOD TO REDUCE PROGRAM NOISE
App. No. 14/500,655
→
DUAL CAPACITOR SENSE AMPLIFIER AND METHODS THEREFOR
App. No. 14/499,717
→
Read With Look-Back Combined With Programming With Asymmetric Boosting In Memory
App. No. 14/500,660
→
BARRIER LAYER STACK FOR BIT LINE AIR GAP FORMATION
App. No. 14/496,360
→
SYSTEMS AND METHODS OF STORING DATA
App. No. 14/495,425
→
3D NAND MEMORY WITH SOCKETED FLOATING GATE CELLS
App. No. 14/494,869
→
DENSE ARRAYS AND CHARGE STORAGE DEVICES
App. No. 14/494,320
→
EFFICIENT WIDE RANGE BIT COUNTER
App. No. 14/492,697
→
THREE DIMENSIONAL MEMORY DEVICE HAVING WELL CONTACT PILLAR AND METHOD OF MAKING THEREOF
App. No. 14/491,026
→
STORAGE DEVICE AND METHOD INCLUDING ACCESSING A WORD LINE OF A MEMORY USING PARAMETERS SELECTED ACCORDING TO GROUPS OF WORD LINES
App. No. 14/489,024
→
MANAGING NON-VOLATILE MEDIA
App. No. 14/486,974
→