IP Library › Granted Patent US 9,336,892

Granted Patent B1

US 9,336,892 · App. 14/728,615 · Granted May 10, 2016

Reducing hot electron injection type of read disturb in 3D non-volatile memory

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Quick Facts

Patent No.: US 9,336,892
App. No.: 14/728,615
Granted: May 10, 2016
Kind: B1

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Abstract

Read disturb due to hot electron injection is reduced in a 3D memory device by controlling the magnitude and timing of word line and select gate ramp down voltages at the end of a sensing operation. In an example read operation, the magnitude of a selected word line voltage is increased to be equal to pass voltages of unselected word lines, and the selected and unselected word line are ramped down at the same time, to avoid creating a channel gradient. In an example verify operation, the above procedure can be followed when the selected word line is at a source-side or middle range among all word lines. When the selected word line is at a drain-side among all word lines, a source-side select gate can be ramped down before the selected word line and a drain-side select gate can be ramped down after the selected word line.

Claims (89)

1. A method for sensing in a memory device, comprising:

applying a demarcation voltage to a selected word line among a plurality of word lines in the memory device, wherein:

the plurality of word lines are connected to memory cells in a plurality of NAND strings,

the plurality of NAND strings comprise a selected NAND string and an unselected NAND string,

the selected NAND string comprises a selected memory cell connected to the selected word line between a drain-side select gate and a source-side select gate,

the unselected NAND string comprises an unselected memory cell connected to the selected word line between a drain-side select gate and a source-side select gate,

a selected source-side select gate line, is connected to the source-side select gate of the selected NAND string,

an unselected source-side select gate line, is connected to the source-side select gate of the unselected NAND string,

a selected drain-side select gate line, is connected to the drain-side select gate of the selected NAND string, and

an unselected drain-side select gate line, is connected to the drain-side select gate of the unselected NAND string;

while the demarcation voltage is applied to the selected word line, a read pass voltage which is higher than the demarcation voltage is applied to unselected word lines among the plurality of word lines, a respective turn-on voltage is applied to the selected source-side select gate line, and a respective turn-on voltage is applied to the selected drain-side select gate line, determining whether the selected memory cell is in a conductive state;

increasing a voltage of the selected word line from the demarcation voltage to an elevated level, the elevated level is within a +/−20% range of the read pass voltage;

concurrently ramping down word line voltages, the concurrently ramping down of the word line voltages comprises ramping down a voltage of the selected word line from the elevated level to a respective steady state voltage and ramping down a voltage of the unselected word lines from the read pass voltage to a respective steady state voltage, while a respective turn-off voltage is applied to the selected source-side select gate line;

ramping down a voltage of the selected source-side select gate line from the respective turn-on voltage to a respective turn-off voltage after the determining whether the selected memory cell is in the conductive state and before the concurrently ramping down of the word line voltages; and

ramping down a voltage of the selected drain-side select gate line from the respective turn-on voltage to a respective turn-off voltage.

2. The method of claim 1 , wherein:

the demarcation voltage is for distinguishing between data states in a read operation; and

the ramping down of the voltage of the selected drain-side select gate line occurs before the concurrently ramping down of the word line voltages.

3. The method of claim 2 , further comprising:

the ramping down of the voltage of the selected drain-side select gate line and the voltage of the selected source-side select gate line, is concurrent, after the determining whether the selected memory cell is in the conductive state and before the concurrently ramping down of the word line voltages.

4. The method of claim 2 , further comprising:

applying a respective turn-off voltage to the unselected drain-side select gate line and a respective turn-off voltage to the unselected source-side select gate line, while the demarcation voltage and the voltage at the elevated level are applied to the selected word line and during the concurrently ramping down of the word line voltages.

5. The method of claim 1 , wherein:

the demarcation voltage is a verify voltage for determining whether the selected memory cell has reached a target data state in a programming operation;

the ramping down of the voltage of the selected drain-side select gate line occurs before the concurrently ramping down of the word line voltages when the selected word line is among a subset of the plurality of word lines, and after the concurrently ramping down of the word line voltages when the selected word line is not among the subset of the plurality of word lines;

the subset of the plurality of word lines comprises source-side and middle word lines but not drain-side word lines among the plurality of word lines; and

the drain-side word lines are adjacent to a drain-side of the selected NAND string and the unselected NAND string and comprises no more than 20% of the plurality of word line.

6. The method of claim 1 , wherein:

the demarcation voltage is a verify voltage for determining whether the selected memory cell has reached a target data state in a programming operation; and

the ramping down of the voltage of the selected drain-side select gate line occurs after the concurrently ramping down of the word line voltages.

7. The method of claim 6 , further comprising:

applying a program voltage to the selected word line in connection with the programming operation after the concurrently ramping down word line voltages; and

during the applying of the program voltage, boosting a channel of the selected NAND string.

8. The method of claim 6 , wherein:

the respective turn-on voltage is applied to the selected drain-side select gate line, while the voltage at the elevated level is applied to the selected word line and during the concurrently ramping down of the word line voltages.

9. The method of claim 6 , further comprising:

for the unselected drain-side select gate line, applying a respective turn-off voltage while the demarcation voltage is applied to the selected word line and applying a respective turn-on voltage while the voltage at the elevated level is applied to the selected word line and during the concurrently ramping down of the word line voltages; and

ramping down a voltage of the unselected drain-side select gate line, from the respective turn-on voltage to the respective turn-off voltage after the ramping down of the voltage of the selected word line and the voltages of the unselected word lines.

10. The method of claim 6 , further comprising:

for the unselected source-side select gate line, applying a respective turn-off voltage while the demarcation voltage and the voltage at the elevated level are applied to the selected word line and during the concurrently ramping down of the word line voltages.

11. The method of claim 1 , wherein:

the selected NAND string comprises a floating body channel; and

the plurality of word lines comprise a plurality of word line layers above one another in a stack, and separated from one another by dielectric layers.

12. A memory device, comprising:

a plurality of word lines connected to memory cells in a selected NAND string, wherein the plurality of word lines comprise a selected word line and unselected word lines, and the selected NAND string comprises a selected memory cell connected to the selected word line between a drain-side select gate and a source-side select gate;

a selected source-side select gate line, connected to the source-side select gate of the selected NAND string;

a selected drain-side select gate line, connected to the drain-side select gate of the selected NAND string; and

a control circuit, the control circuit is configured to:

apply a demarcation voltage to the selected word line, wherein the demarcation voltage is for distinguishing between data states in a read operation;

while the demarcation voltage is applied to the selected word line and while a read pass voltage which is higher than the demarcation voltage is applied to unselected word lines among the plurality of word lines, and while a respective turn-on voltage is applied to the selected source-side select gate line, and a respective turn-on voltage is applied to the selected drain-side select gate line, make a determination of whether the selected memory cell is in a conductive state;

increase a voltage of the selected word line from the demarcation voltage to an elevated level;

to perform a word line ramp down, concurrently ramp down the voltage of the selected word line from the elevated level to a respective steady state voltage and ramp down the voltage of the unselected word lines from the read pass voltage to a respective steady state voltage; and

after the determination of whether the selected memory cell is in the conductive state and before the word line ramp down, perform a select gate line ramp down, wherein the control circuit, to perform the select gate line ramp down, is configured to concurrently ramp down a voltage of the selected drain-side select gate line, from the respective turn-on voltage to a respective steady state voltage and a voltage of the selected source-side select gate line, from the respective turn-on voltage to a respective turn-off voltage.

13. The memory device of claim 12 , further comprising:

an unselected NAND string comprising an unselected memory cell connected to the selected word line between a drain-side select gate and a source-side select gate;

an unselected source-side select gate line, connected to the source-side select gate of the unselected NAND string; and

an unselected drain-side select gate line, connected to the drain-side select gate of the unselected NAND string, wherein the control circuit is configured to apply a respective turn-off voltage to the unselected drain-side select gate line, and a respective turn-off voltage to the unselected source-side select gate line, while the demarcation voltage and the voltage at the elevated level are applied to the selected word line and during the word line ramp down and the select gate line ramp down.

14. The memory device of claim 12 , wherein:

the selected NAND string comprises a floating body channel; and

the plurality of word lines comprise a plurality of word line layers above one another in a stack, and separated from one another by dielectric layers.

15. The memory device of claim 12 , wherein:

the respective steady state voltage the respective steady state voltage the respective turn-off voltage and the respective turn-off voltage are 0 V.

16. The memory device of claim 12 , wherein:

the elevated level is within a +/−20% range of the read pass voltage.

17. A method for sensing in a memory device, comprising: