Single-stage folded cascode buffer amplifiers with analog comparators

1. A single-stage folded cascode buffer comprising:

an amplifier having a first input terminal, a second input terminal, and an output terminal coupled to the second input terminal of the amplifier;

a first analog comparator comprising a first input terminal coupled to the second input terminal of the amplifier, a second input terminal coupled to the first input terminal of the amplifier, and an output terminal;

a second analog comparator comprising a first input terminal coupled to the second input terminal of the amplifier, a second input terminal coupled to the first input terminal of the amplifier, and an output terminal;

a first transistor comprising a first terminal coupled to a positive supply terminal, a second terminal coupled to the output terminal of the first analog comparator, and a third terminal coupled to the output terminal of the amplifier; and

a second transistor comprising a first terminal coupled to the output terminal of the amplifier, a second terminal coupled to the output terminal of the second analog comparator, and a third terminal coupled to a negative supply terminal.

2. The single-stage folded cascode buffer of claim 1 , wherein the amplifier comprises a single-stage folded cascode amplifier.

3. The single-stage folded cascode buffer of claim 1 , wherein the first analog comparator comprises a first input-referred offset voltage δV 1 .

4. The single-stage folded cascode buffer of claim 3 , wherein the first input-referred offset voltage δV 1 is between about 25 mV and about 50 mV.

5. The single-stage folded cascode buffer of claim 1 , wherein the second analog comparator comprises a second input-referred offset voltage δV 2 .

6. The single-stage folded cascode buffer of claim 5 , wherein the second input-referred offset voltage δV 2 is between about 25 mV and about 50 mV.

7. The single-stage folded cascode buffer of claim 1 , wherein the first transistor is configured to turn ON in response to a positive slewing transient on the first input terminal of the amplifier.

8. The single-stage folded cascode buffer of claim 1 , wherein the first transistor is configured to be OFF when a difference between a voltage at the first input terminal of the amplifier and a voltage at the output terminal of the amplifier is less than a first predetermined value.

9. The single-stage folded cascode buffer of claim 1 , wherein the second transistor is configured to turn ON in response to a negative slewing transient on the first input terminal of the amplifier.

10. The single-stage folded cascode buffer of claim 1 , wherein the second transistor is configured to be OFF when a difference between a voltage at the first input terminal of the amplifier and a voltage at the output terminal of the amplifier is less than a second predetermined value.

11. A single-stage folded cascode buffer comprising:

an amplifier comprising a first input terminal, a second input terminal, an output terminal, a first input differential pair, a second input differential pair, and a cascode output stage, the first input differential pair and the second input differential pair coupled to the first input terminal and the second input terminal of the amplifier, the cascode output stage coupled to the first input differential pair, the second input differential pair, and the output terminal of the amplifier, which is coupled to the second input terminal of the amplifier;

a first analog comparator comprising a first input terminal, a second input terminal, an output terminal, a third input differential pair, and a first load stage, the third input differential pair coupled to the first input terminal and the second input terminal of the first analog comparator, and the first input terminal and the second input terminal of the amplifier, and the first load stage coupled to the third input differential pair and the output terminal of the first analog comparator;

a second analog comparator comprising a first input terminal, a second input terminal, an output terminal, a fourth input differential pair, and a second load stage, the fourth input differential pair coupled to the first input terminal and the second input terminal of the second analog comparator, and the first input terminal and the second input terminal of the amplifier, and the second load stage coupled to the fourth input differential pair and the output terminal of the second analog comparator;

a first transistor comprising a first terminal coupled to a positive supply terminal, a second terminal coupled to the output terminal of the first analog comparator, and a third terminal coupled to the output terminal of the amplifier; and

a second transistor comprising a first terminal coupled to the output terminal of the amplifier, a second terminal coupled to the output terminal of the second analog comparator, and a third terminal coupled to a negative supply terminal.

12. The single-stage folded cascode buffer of claim 11 , wherein the first analog comparator comprises a first input-referred offset voltage δV 1 .

13. The single-stage folded cascode buffer of claim 12 , wherein the first input-referred offset voltage δV 1 is between about 25 mV and about 50 mV.

14. The single-stage folded cascode buffer of claim 11 , wherein the second analog comparator comprises a second input-referred offset voltage δV 2 .

15. The single-stage folded cascode buffer of claim 14 , wherein the second input-referred offset voltage δV 2 is between about 25 mV and about 50 mV.

16. The single-stage folded cascode buffer of claim 11 , wherein the first transistor is configured to turn ON in response to a positive slewing transient on the first input terminal of the amplifier.

17. The single-stage folded cascode buffer of claim 11 , wherein the first transistor is configured to be OFF when a difference between a voltage at the first input terminal of the amplifier and a voltage at the output terminal of the amplifier is less than a first predetermined value.

18. The single-stage folded cascode buffer of claim 11 , wherein the second transistor is configured to turn ON in response to a negative slewing transient on the first input terminal of the amplifier.

19. The single-stage folded cascode buffer of claim 11 , wherein the second transistor is configured to be OFF when a difference between a voltage at the first input terminal of the amplifier and a voltage at the output terminal of the amplifier is less than a second predetermined value.

20. A method for providing a single-stage folded cascode buffer, the method comprising:

providing an amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the amplifier comprises a single-stage folded cascode amplifier;

providing a first analog comparator comprising a first input terminal, a second input terminal and an output terminal;

providing a second analog comparator comprising a first input terminal, a second input terminal and an output terminal;

providing a first transistor comprising a first terminal, a second terminal and a third terminal;

providing a second transistor comprising a first terminal, a second terminal and a third terminal;

coupling the output terminal of the amplifier to the second input terminal of the amplifier;

coupling the first input terminal of the first analog comparator and the first input terminal of the second analog comparator to the second input terminal of the amplifier;

coupling the second input terminal of the first analog comparator and the second input terminal of the second analog comparator to the first input terminal of the amplifier;

coupling the first terminal of the first transistor to a positive supply terminal, coupling the second terminal of the first transistor to the output terminal of the first analog comparator, and coupling the third terminal of the first transistor to the output terminal of the amplifier; and

coupling the first terminal of the second transistor to the output terminal of the amplifier, coupling the second terminal of the second transistor to the output terminal of the second analog comparator, and coupling the third terminal of the second transistor to a negative supply terminal.

21. The method of claim 20 , wherein the first analog comparator comprises a first input-referred offset voltage δV 1 .

22. The method of claim 21 , wherein the first input-referred offset voltage δV 1 is between about 25 mV and about 50 mV.

23. The method of claim 20 , wherein the second analog comparator comprises a second input-referred offset voltage δV 2 .

24. The method of claim 23 , wherein the second input-referred offset voltage δV 2 is between about 25 mV and about 50 mV.

25. The method of claim 20 , further comprising turning ON the first transistor in response to a positive slewing transient on the first input terminal of the amplifier.

26. The method of claim 20 , further comprising keeping the first transistor OFF when a difference between a voltage at the first input terminal of the amplifier and a voltage at the output terminal of the amplifier is less than a first predetermined value.

27. The method of claim 20 , further comprising turning ON the second transistor in response to a negative slewing transient on the first input terminal of the amplifier.

28. The method of claim 20 , further comprising keeping the second transistor OFF when a difference between a voltage at the first input terminal of the amplifier and a voltage at the output terminal of the amplifier is less than a second predetermined value.